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 custom inductor/tline layout Assura LVS issue 

Last post Fri, May 2 2014 8:10 AM by manula21. 2 replies.
Started by snaildr 30 Apr 2012 05:31 AM. Topic has 2 replies and 2639 views
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  • Mon, Apr 30 2012 5:31 AM

    • snaildr
    • Not Ranked
    • Joined on Sun, Mar 25 2012
    • Seattle, WA
    • Posts 5
    • Points 55
    custom inductor/tline layout Assura LVS issue Reply
    Hi there,
     
    I need to incorporate a few custom designed transmission lines and inductors in to a TSMC 65nm tapeout. I found a document from another TSMC pdk about using Assura ?blackboxcell option to do LVS and RCX. The basic procedure is that you copy n2port element into the PDK lib and name it as a new cell (for example n2port_d1). Then copy symbol view to auLvs and auCdl views, do some editing in CDF. Next, create layout view for this cell with pins matching n2port _d1(which are t1, b1, t2, b2). In the higher level tapeout, when doing LVS, list n2port_d1 cell in the ?blackboxcell option. My problem is that Assura goes into n2port_d1 cell and decide the pins (t1, b1, t2, b2) are floating and discarded all of them. Then Assura discovered these pins are missing in layout, and terminated the LVS.
     
    Here is how my runName.erc file looks like
     

    ***** Begin Label Report *****

     Label in cell 'nmos_rf layout tsmcN65 macro="nmos_rf"':
      info: Assign pin label "S" at (2.520, 1.000) to layer `metal4'.
      info: Assign pin label "G" at (2.520, 2.180) to layer `metal3'.
      info: Assign pin label "D" at (2.520, -0.530) to layer `metal2'.
      info: Assign pin label "B" at (5.855, 1.000) to layer `metal1'.

     Label in cell 'n2port_d1 layout tsmcN65':
      info: Floating label discarded:  "t1" at (1.200, 0.500).
      info: Floating label discarded:  "t2" at (153.300, -1.200).
      info: Floating label discarded:  "b2" at (153.300, -8.400).
      info: Floating label discarded:  "b1" at (0.700, -8.500).
      info: Floating label discarded:  "t2" at (153.400, -1.200).
      info: Floating label discarded:  "t1" at (1.200, 0.500).
      info: Floating label discarded:  "b2" at (153.400, -8.300).
      info: Floating label discarded:  "b1" at (0.800, -8.400).

     Label in cell 'TL_test1_core layout tsmc65debug':
      info: Assign pin label "P1" at (56.100, -208.950) to layer `metal3'.
      info: Assign pin label "P2" at (54.550, -38.600) to layer `metal3'.
      info: Assign pin label "gnd!" at (49.600, -205.800) to layer `metal2'.
      info: Assign pin label "vdd!" at (54.350, -43.400) to layer `metal2'.

    ***** End of Label Report *****
     
     
    My problem seems similar to the one discussed in this thread, but I didn't find a final answer
    http://www.cadence.com/Community/forums/p/14022/22986.aspx#22986 
     
     
    I'd appreciate your input. Also, could you please point me to relevant reference documents where I could learn more about how to do custom cell LVS and extraction with Assura and Calibre?
     
    thanks,
    Ran 
    • Post Points: 20
  • Wed, May 2 2012 1:22 PM

    • snaildr
    • Not Ranked
    • Joined on Sun, Mar 25 2012
    • Seattle, WA
    • Posts 5
    • Points 55
    Re: custom inductor/tline layout Assura LVS issue Reply

    I figured this out, the cause is that pinLayer definition in extract.rul is missing, the file require a few edits, relevant informantion can be found in Assura Developer Guide. Thanks for your attention. If you have trouble with this too, I'd be gald to help out.

     Ran 

    • Post Points: 5
  • Fri, May 2 2014 8:10 AM

    • manula21
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    • Joined on Sun, Oct 13 2013
    • Posts 1
    • Points 5
    Re: custom inductor/tline layout Assura LVS issue Reply

    Hi,

    I am having a same problem in running LVS on custom designed inductor.Can you  explain what do you mean by "some editing in CDF".

    • Post Points: 5
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Started by snaildr at 30 Apr 2012 05:31 AM. Topic has 2 replies.