That's the issue to pass LEC.
I use synopsys DFT Compiler to insert scan chain for synthesis netlist from RTL Compiler.
When I compare the synthesis netlist from RTL Compiler and the scan netlist from DFT Compiler.
I found some non-eq on scan flops.
Below is a scan cell RTL Compiler generated.
SDFCNQD1BWP12TNDO35CDM4NMLVT uck_reset_b_n_sync_q1_reg_0(.CDN (n_2),
.CP (ck_gclkcr), .D (uck_reset_b_n_sync_q0), .SI (ck_reset_b_n),
.SE (ck_reset_f_n), .Q (ck_reset_b_n));
I think scan replacement during synthesis is OK for me.
But I wnat all the scan cell pin - SE is tied to 0, and SI also is tied to 0.
I can't find correct options in RTL Compiler to do this.
Do you have any ideas for this?