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 High frequency quadrature VCO design with good phase noise 

Last post Thu, Mar 29 2012 7:10 PM by rohan kr. 0 replies.
Started by rohan kr 29 Mar 2012 07:10 PM. Topic has 0 replies and 2586 views
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  • Thu, Mar 29 2012 7:10 PM

    • rohan kr
    • Not Ranked
    • Joined on Wed, Mar 28 2012
    • Melbourne, Victoria
    • Posts 10
    • Points 110
    High frequency quadrature VCO design with good phase noise Reply

    Hello everyone

    I am a newbie engineer starting my career in RF IC design and working on designing a high frequency VCO (38 GHz) with good phase noise characteristics. I am using Cadence IC6.1.5-64b.500 version and spectre simulator for the schemtic design and simulations. I have to do everything from design to verification to layout to LVS by myself..It's just been a very tough month especially because I am an amateur (I did work on a neural amplifier but that was low freq) and also because oscillators are very tricky with lots of parameters to look at..I am genuinely a fan of some of the members here and the insight & experience  that they have...

    I have created this separate post for my VCO design because it's really cumbersome to put different problems of same circuit in different posts and to keep on referring..It's easier for me and for others to follow especially new people like me..& I will be putting problem numbers & hoping you would do the same while referring so that members can address them easily with numbers.. If I have a very specific problem I will be putting it as a separate post and giving the url...

    The circuit schematic I am using is as below..Its an quadrature LC vco with nmos-pmos structure..the mos acts as a doubler doubling the 19 Ghz signal..

    Problem1 - Phase noise : Please refer to http://www.cadence.com/community/forums/T/22045.aspx  

    Problem1 - PMOS : I am  having trouble getting quadrature output..i.e. the I and Q signals run in phase right now...Earlier the pmos transistors in my circuit were having w/l as 100u/60n and the nmos were 25u/60n ..at that time  i was getting good quadrature phase....but now i reduced the size of all trans (which my supervisor suggested was very big and told me to increase L and C values) to almost 45u/60n....The pmos transistors should act as doubler are in cutoff and  so the transient waveform has a dc level at 1.5 V(which is the supply voltage)..

    Problem2 - Signal swing : the transient waveform has a dc level at 1.5 V(which is the supply voltage)...I am not sure if this is correct even though the signal swing I am getting is nearly 1 V or even more..I know it shouldn't be this high..also if i connect a port to i+ and i- terminal with resistance of 100ohm , the swing just reduces a lot..i know the circuit needs a buffer afterwards..will that solve this prob..

    Thanks in Advance..

    Rohanmort !! 

     


    • Post Points: 5
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Started by rohan kr at 29 Mar 2012 07:10 PM. Topic has 0 replies.