From your post, I’m not sure if your design is NEQ.
If your design is EQ, you can just let LEC figure out the mapping. The tool might run a little longer to resolve the mapping but it will be automatic.
If your design is not-EQ or mapping takes a long time first consider why the key-points are not mapping by name. Ask yourself, between the two gate netlists, what could have been optimized or changed? (E.g. clock gating changes, register cloning, etc.) To show the key points that aren’t mapping by name run with set_mapping_method –name only.
This is described in the Cadence support post (solution) here:
Mapping consists of two stages. One is a quick name-based mapping and the second is a functional mapping. Functional mapping takes longer. (This is why you may see mapping quickly go to 98% but then take longer to resolve the last 2%. )
Renaming rules aren’t often required but in this case it could help. (This is also described in the previous link.)
Finally, if the mapping is bad then you can try remapping or phase mapping (debug shows this is needed). This is described here:http://support.cadence.com/wps/mypoc/cos?uri=deeplinkmin:ViewSolution;solutionNumber=11514542
Let the list know if this helped.