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 pcell problem 

Last post Mon, Mar 26 2012 7:56 AM by Stefan Bormann. 1 replies.
Started by Stefan Bormann 26 Mar 2012 06:31 AM. Topic has 1 replies and 1583 views
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  • Mon, Mar 26 2012 6:31 AM

    pcell problem Reply


    I have the following question.

    I updated our pdk (tsmc process) with some addons for rf devices and minor techlib tweaks.

    We have some special capacitors  (crtmom). The pcell for this is working good, but

    if I open an old layout with pcells from before the chance I miss some layers (VIA2 and MET2).

    The strange things is this:

    In the same layout I have both types of the layouts (created by the pcell before and after the change).

    1) copying/editing the new one all is correct, also if I insert it from the techlib as a new part.

    2) copying/editing the old oneit still have the old layout (without MET2 / VIA2) inserting a part again from the techlib (the same cell as in step1) it comes with the wrong layout (without MET2/VIA2)

     copying cell to another cell with different name doesn't help.

    that means replacing  hierachical is not working.


    Any ideas how I can virtuoso force to use the correct pcell?

    Thanks in advance.


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    • Post Points: 5
  • Mon, Mar 26 2012 7:56 AM

    Re: pcell problem Reply


    I found the error,

    I had to rerun a tsmc script on the pdk library to generate the pcells.

    So the problem was the pcell.

    Now it is working as it should.



    • Post Points: 5
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Started by Stefan Bormann at 26 Mar 2012 06:31 AM. Topic has 1 replies.