Home > Community > Forums > Functional Verification > Beginner: ncvlog: *E,NOTSTT (/design/notebook/bp07/users/cinzia.cicchillitti+bp07+bp07a+41/cds5/BP07/BP07STARTUP/verilogams/verilog.vams,34|7): expecting a statement [9(I

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 Beginner: ncvlog: *E,NOTSTT (/design/notebook/bp07/users/cinzia.cicchillitti+bp07+bp07a+41/cds5/BP07/BP07STARTUP/verilogams/verilog.vams,34|7): expecting a statement [9(I 

Last post Thu, Mar 22 2012 7:16 AM by whiteriver. 1 replies.
Started by mrmzz 22 Mar 2012 05:50 AM. Topic has 1 replies and 3077 views
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  • Thu, Mar 22 2012 5:50 AM

    • mrmzz
    • Not Ranked
    • Joined on Thu, Mar 22 2012
    • Posts 2
    • Points 40
    Beginner: ncvlog: *E,NOTSTT (/design/notebook/bp07/users/cinzia.cicchillitti+bp07+bp07a+41/cds5/BP07/BP07STARTUP/verilogams/verilog.vams,34|7): expecting a statement [9(I Reply

     I need a support for subject errr for a very simple code

     

     

    //Verilog-AMS HDL for "BP07", "BP07STARTUP" "verilogams"

    `include "constants.vams"
    `include "disciplines.vams"

    // Modification History :
    // Initial Release        Mar 21 16:16:43 2012
    // owner            cici
    //
    // ISSUE:
    //   To model real saturation the pins should be defined inout
    //   but this is not the case
    //

    module BP07STARTUP ( INP5UN, INP5UN_LKG, IT1UN, ITP5UN_BS, G, IN );

      input G;             wreal G;
      input IN;             wreal IN;
      output  [0:3] INP5UN;     wreal INP5UN[0:3];
      output ITP5UN_BS;         wreal ITP5UN_BS;
      output INP5UN_LKG;         wreal INP5UN_LKG;
      output  [7:0] IT1UN;         wreal IT1UN[7:0];

     
      real Ival1u;
      real Ival500n;
      real Vsat = 200m;
      real Rsh  = 1e12 ;

     always @(IN )
        if(IN > 2 ) begin
             Ival1u = 1u;
          Ival500n = 500n;
        else begin
             Ival1u = 0;
         Ival500n = 0;
       end

      assign ITP5UN_BS = Ival500n;
      assign INP5UN_LKG = Ival500n;
      assign INP5UN[0] = Ival500n;
      assign INP5UN[1] = Ival500n;
      assign INP5UN[2] = Ival500n;
      assign INP5UN[3] = Ival500n;
      assign IT1UN[0] = Ival1u;
      assign IT1UN[1] = Ival1u;
      assign IT1UN[2] = Ival1u;
      assign IT1UN[3] = Ival1u;
      assign IT1UN[4] = Ival1u;
      assign IT1UN[5] = Ival1u;
      assign IT1UN[6] = Ival1u;
      assign IT1UN[7] = Ival1u;

    endmodule

     

     

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    • Post Points: 20
  • Thu, Mar 22 2012 7:16 AM

    • whiteriver
    • Not Ranked
    • Joined on Mon, Apr 19 2010
    • Posts 6
    • Points 45
    Re: Beginner: ncvlog: *E,NOTSTT (/design/notebook/bp07/users/cinzia.cicchillitti+bp07+bp07a+41/cds5/BP07/BP07STARTUP/verilogams/verilog.vams,34|7): expecting a statement [9(I Reply

    you forgot the 'end' for your if block. You should modify it like this:

     

    always @(IN )

        if(IN > 2 ) begin

             Ival1u = 1u;

          Ival500n = 500n;

        end 

        else begin 

             Ival1u = 0;

         Ival500n = 0;

       end

     

    • Post Points: 5
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Started by mrmzz at 22 Mar 2012 05:50 AM. Topic has 1 replies.