I need a support for subject errr for a very simple code
//Verilog-AMS HDL for "BP07", "BP07STARTUP" "verilogams"
`include "constants.vams"
`include "disciplines.vams"
// Modification History :
// Initial Release Mar 21 16:16:43 2012
// owner cici
//
// ISSUE:
// To model real saturation the pins should be defined inout
// but this is not the case
//
module BP07STARTUP ( INP5UN, INP5UN_LKG, IT1UN, ITP5UN_BS, G, IN );
input G; wreal G;
input IN; wreal IN;
output [0:3] INP5UN; wreal INP5UN[0:3];
output ITP5UN_BS; wreal ITP5UN_BS;
output INP5UN_LKG; wreal INP5UN_LKG;
output [7:0] IT1UN; wreal IT1UN[7:0];
real Ival1u;
real Ival500n;
real Vsat = 200m;
real Rsh = 1e12 ;
always @(IN )
if(IN > 2 ) begin
Ival1u = 1u;
Ival500n = 500n;
else begin
Ival1u = 0;
Ival500n = 0;
end
assign ITP5UN_BS = Ival500n;
assign INP5UN_LKG = Ival500n;
assign INP5UN[0] = Ival500n;
assign INP5UN[1] = Ival500n;
assign INP5UN[2] = Ival500n;
assign INP5UN[3] = Ival500n;
assign IT1UN[0] = Ival1u;
assign IT1UN[1] = Ival1u;
assign IT1UN[2] = Ival1u;
assign IT1UN[3] = Ival1u;
assign IT1UN[4] = Ival1u;
assign IT1UN[5] = Ival1u;
assign IT1UN[6] = Ival1u;
assign IT1UN[7] = Ival1u;
endmodule