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 CCD check fails as Encounter cannot parse a design file which has a "generate" block in it 

Last post Thu, Mar 15 2012 2:30 AM by dp2402. 6 replies.
Started by dp2402 14 Mar 2012 06:40 AM. Topic has 6 replies and 3344 views
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  • Wed, Mar 14 2012 6:40 AM

    • dp2402
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    CCD check fails as Encounter cannot parse a design file which has a "generate" block in it Reply

    Hello all,

    I am currently running a CONFORMAL (R) Constraint Designer v10.10 check for an IP which consists several *.v files.

    In one of the .v files the "generate" statement has been used -- This is causing an error while I run my CCD script.

    -----------------
    Error msg given by compiler:

    // Parsing file ~hdl/abc.v ...
    // Error: hdl_default_checks/rtl_checks/RTL13.6: Standalone generated blocks are not supported in the IEEE standard
    // In line 235, file '~hdl/abc.v'
    // Error: Fail to read design.
    // Read design summary: Error: 1, Warning: 0, Note: 0
    -----------------

    CCD script which reads the design file:

    read design -verilog2k -define <company_tech_name>\
    -root <....> \
    -parameter <...> \
    hdl/some_file.v \
    hdl/abc.v \
    hdl/some_file.v \
    -lastmod -noelab

    -------------------------

    Please throw some light on the RTL13.6 error message and tell me which switch I shall use witn the "read design" command so that the error message regarding use of "generate" statement in design dosen't show up?

    Hope I am clear in the explanation!

    Thanks

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    • Post Points: 20
  • Wed, Mar 14 2012 6:51 AM

    • Shalom B
    • Top 200 Contributor
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    • Jerusalem, 00-IL
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    Re: Getting problem with CCD check due to use of "generate" block in one design file Reply

    A standalone generate block is one in which the generate construct contains content outside a generate-if/case/for.

     Example:

    generate

    wire x;

    endgenerate

    The 'wire x;' declaration does not appear inside a generate if/for/case.

    This is legal in Verilog-2001, but not in Verilog-2005 and SystemVerilog.

    Maybe Conformal has a switch to tell it to use the 2001 version instead of the 2005 versio.

    Or you can tell Conformal to treat this as a warning instead of an error.

    Shalom

    Shalom.Bresticker@intel.com
    • Post Points: 20
  • Wed, Mar 14 2012 6:59 AM

    • dp2402
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    Re: Getting problem with CCD check due to use of "generate" block in one design file Reply

    Yes, that's what I believe too, that the "read design" must be having a switch!

    You see in my 1st post, I am already using the switch " -verilog2k  " but that dosen't solve the problem.

    I have checked the Conformal_Ref.pdf documentation for all switches belonging to the cmd "read design", but couldn't find it there.

    Also it is no use changing an Error to a Warning! Coz if my script cannot parse the design file, it is no use running the constraint.

    I am using CCD for the 1st time & have no experience!

    • Post Points: 20
  • Wed, Mar 14 2012 8:54 AM

    • croy
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    Re: Getting problem with CCD check due to use of "generate" block in one design file Reply

    R&D made RTL13.6 an error in 10.1. It went back to a warning within 2 months. You could download 11.1 or do 'set rule handling RTL13.6 -warning' if continuing with 10.1.

     

    Chrystian

    • Post Points: 20
  • Wed, Mar 14 2012 10:06 AM

    • dp2402
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    Re: Getting problem with CCD check due to use of "generate" block in one design file Reply

    Hi Chrystian,

    Just when I thought my problem is solved, CCD now says that RTL13.6 is an unknown rule!

    But if I run the script without the 'set rule handling ....', compiler gives error:

    // Error: hdl_default_checks/rtl_checks/RTL13.6: Standalone generated blocks are not supported in the IEEE standard

    :(  Can't understand what's happening!

     

    • Post Points: 20
  • Wed, Mar 14 2012 10:55 AM

    • croy
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    Re: Getting problem with CCD check due to use of "generate" block in one design file Reply

    Please use 10.10-s280 or later.

    set rule handling hdl_default_checks/rtl_checks/RTL13.6 -severity warning

    Chrystian

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  • Thu, Mar 15 2012 2:30 AM

    • dp2402
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    Re: Getting problem with CCD check due to use of "generate" block in one design file Reply

    Thanks a lot  Chrystian.

    Works perfectly!

    • Post Points: 5
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Started by dp2402 at 14 Mar 2012 06:40 AM. Topic has 6 replies.