First, please follow the guidelines and not append to a post that has had no traffic in over 6-months.
Strictly speaking the iterated instance (e.g. I0<0:3>) represents separate devices connected in parallel, and the m-factor is a parameter passed to the simulator to model a single component as multiple devices connected in parallel, without adding further complexity to the netlist or simulation matrix (i.e. in this example 1 device with m=4 is a single device in the netlist but an instance with <0:3> in the name is 4 devices connected in parallel, yielding 4 devices in the netlist). When converting a schematic into a layout both should yield the same number of transistors, so in this regard they are the same, but for simulation I think that the m-factor approach reduces netlist and simulation complexity.