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 incomplete nets 

Last post Wed, Nov 7 2012 1:19 PM by nimay. 6 replies.
Started by crystee 23 Feb 2012 12:26 AM. Topic has 6 replies.
Page 1 of 1 (7 items)
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  • Thu, Feb 23 2012 12:26 AM

    • crystee
    • Not Ranked
    • Joined on Tue, Feb 21 2012
    • Posts 12
    • Points 225
    incomplete nets Reply

    Hi all,

    i am working with soc -encounter. while routing the design no violations were reported.
    but when verified with calibre -lvs its showing 4 incomplete nets. when checked for same nets in soc - E those are no connected/routed as required.
    what would be the reason & how to overcome such violations.

    should these nets must be routed manually?

    Thanks
    • Post Points: 35

  • Mon, Feb 27 2012 1:00 AM

    • Anjana
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    • Joined on Wed, Feb 22 2012
    • Posts 12
    • Points 135
    Re: incomplete nets Reply

    Yes , route them manually
    • Post Points: 5

  • Mon, Feb 27 2012 7:12 AM

    • wally1
    • Top 50 Contributor
    • Joined on Mon, Aug 4 2008
    • <?xml version="1.0" encoding="utf-16"?><string>Bellevue, WA</string>
    • Posts 125
    • Points 2,440
    Re: incomplete nets Reply

    If you run Verify Connectivity in Encounter do these nets get reported as open? If they do, NanoRoute should route them assuming they are signal nets and they have not been excluded from routing (setAttribute -net netName -skip_routing true). If Verify Connectivity does not report the open then double check that the Verilog netlist defines the connectivity. If these are power/ground nets make sure globalNetConnect was run to define their connectivity and use power planning commands (addRing, addStripe, sroute) to route them.

    Regards,

    Brian

    • Post Points: 20

  • Tue, Feb 28 2012 12:10 AM

    • crystee
    • Not Ranked
    • Joined on Tue, Feb 21 2012
    • Posts 12
    • Points 225
    Re: incomplete nets Reply

    Verify Connectivity does not report any violations. When taken to calibre for LVS, these nets are reported as incomplete.

    When checked back in SoC-E these are not connected as intended.

    These are not power/ground nets.
    • Post Points: 20

  • Tue, Feb 28 2012 8:53 AM

    • Kari
    • Top 10 Contributor
    • Joined on Tue, Jul 15 2008
    • Cary, NC
    • Posts 651
    • Points 12,995
    Re: incomplete nets Reply

    what does one of these nets look like in the verilog or def?

    try running verify connectivity on the specific net name.

    not sure what's going on, just some ideas to try...
    • Post Points: 20

  • Wed, Feb 29 2012 3:19 AM

    • crystee
    • Not Ranked
    • Joined on Tue, Feb 21 2012
    • Posts 12
    • Points 225
    Re: incomplete nets Reply

    Hi all,

    Thanks for your suggestions, finaly found out the reason behind the problem.

    The netlist provided was not made case-sensitive. In design which were reported as incomplete nets are all case senstive.

    This we can found out by checking in Tools --> schematic viewer of SoC-E.

    When i tried it showed 2 nets of same name with case sensitivity like N97 & n97. By making the netlist case sensitive the problem is solved.

    Thanks
    • Post Points: 20

  • Wed, Nov 7 2012 1:19 PM

    • nimay
    • Not Ranked
    • Joined on Fri, Jul 29 2011
    • Posts 1
    • Points 5
    Re: incomplete nets Reply

     Hi,

    How did you make your netlist case sensitive?

    Nimay

    • Post Points: 5
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Started by crystee at 23 Feb 2012 12:26 AM. Topic has 6 replies.