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 Cadence noise aware PLL design flow: have lock problem 

Last post Tue, Feb 7 2012 3:40 PM by lunren. 9 replies.
Started by lunren 06 Feb 2012 04:16 PM. Topic has 9 replies and 4998 views
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  • Mon, Feb 6 2012 4:16 PM

    • lunren
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    Cadence noise aware PLL design flow: have lock problem Reply
    Hi All,

    It is a bit long story. I will try my best to explain it clear. Thanks for your patience to read it through and give me some feedback.
    Recently I tried to follow Cadence noise-aware PLL design flow (PLL Macro Model Wizard) to verify my design. (We got the PLL_workshop from Cadence already) I think I successfully extracted VCO (oscmm), pfd+cp (pllTTpfd_cp) models. Then in 1st step, I run pll bench. It doesn't lock, vtune keeps going up. I think maybe I need to swap Fref and Fcomp (though I knew it is not correct to do so) to see what will happen. It turned out that the loop locks and I got correct phase noise curve which matches my simulation results (combining block noise with matlab) very well.

    My interests are to see power supply noise effects on phase noise. So in 2nd step, I re-run the simulation with VCO model "oscmm_vdd". However the loop doesn't lock. I swapped Fref and Fcomp back, it still doesn't lock and vtune keeps going up. Then I replaced VCO model with "oscmm" and tried to reproduce what I got in 1st step, however the loop can't get locked whatever I played with Fref and Fcomp. I replaced model pllTTpfd_cp with transistor design, it locks. So I think there is some problem with the extracted model of pfd+cp. I re-extracted the model for pfd+cp (flowing the flow), but the problem doesn't get solved.

    Then I paid more attention to how the pfd+cp model was get extracted. From the log file, I found that (can find how to attach file, just type here :

     PFD-CP model parameters:
    Iup_max=5.38213 uA
    Idown_max=965.764 nA
    uptr=705.426 ps
    downtr=23.0264 ps
    refdelay=647.335 ps
    fbdelay=658.021 ps
    dir=1
    Vtrans=1 V.

    To me, it seems the extracted model is not correct since Iup_max and Idown_max are not equal and the number is not correct (should be 100uA). Then I run simulation to extract the pfd+cp model for cell "pfd_cp_bench" provided by Cadence in library "PLL_workshop", what I got is:

    Iup_max=662.46 uA
    Idown_max=4.18422 mA
    uptr=1.78008 ns
    downtr=551.137 ps
    refdelay=2.11229 ns
    fbdelay=802.128 ps
    dir=1
    Vtrans=1 V.

    It seems the extracted model have the same problem: Iup_max and Idown_max are not equal (I verified that the current should be 4mA). But the pll_bench from library "PLL_workshop" have no lock problem.

    I am wondering why my pll model doesn't lock and how to deal with this problem. If you need more information, please let me know.

    Thanks a lot.

    Lunren
    • Post Points: 20
  • Mon, Feb 6 2012 4:22 PM

    • lunren
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    Re: Cadence noise aware PLL design flow: have lock problem Reply
    I don't know why several paragraphs were merged into one paragraph. It makes the post harder to read. Sorry for that.
    • Post Points: 5
  • Mon, Feb 6 2012 4:24 PM

    • Tawna
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    RE: Cadence noise aware PLL design flow: have lock problem Reply
    Hi Lunren,
     
    I think it is best to file a Service Request for this sort of question. (http://support.cadence.com)
    The PLL Noise Aware flow requires special permissions to access it.
     
    Best regards,
     
    Tawna Wilsey
    Best regards, Tawna Wilsey Staff Support AE, Global Customer Support Cadence Design Systems, Inc.
    • Post Points: 20
  • Mon, Feb 6 2012 4:34 PM

    • lunren
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    Re: RE: Cadence noise aware PLL design flow: have lock problem Reply
    Hi Tawan, What do you mean by special permission to access PLL Noise Aware flow? I thought we need special permission (or license) to get library "PLL_workshop", but it is not PLL Noise Aware flow needs special permission, is it? We did asked Cadence permission for library "PLL_workshop" last year and of course it already expires.
    Filed under:
    • Post Points: 20
  • Mon, Feb 6 2012 5:41 PM

    • Tawna
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    RE: RE: Cadence noise aware PLL design flow: have lock problem Reply
    Hi Lunren,
     
    To get the actual PLL Noise Aware flow workshop library, you need to sign an SPLA and Kit exhibit (your Sales AE can assist you with this.)   
     
    To just use the documentation for the PLL Noise Aware Flow, it is available in the Spectre hierarchy at:
     
    <path_to>/MMSIM111ISR/tools.lnx86/spectre/examples/SpectreRF_workshop/PLL.pdf
     
     
    best regards,
     
    Tawna
    Best regards, Tawna Wilsey Staff Support AE, Global Customer Support Cadence Design Systems, Inc.
    • Post Points: 20
  • Mon, Feb 6 2012 9:03 PM

    • lunren
    • Top 500 Contributor
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    Re: RE: RE: Cadence noise aware PLL design flow: have lock problem Reply
    Hi Tawna, My problem is not to get "PLL_workshop" library and the doc "PLL.pdf". My problem is that after I flow the PLL Noise Aware Flow, the loop doesn't lock. I think the pfd+cp extraction model has some problem which cause the PLL fail to lock. I need some help on this.
    • Post Points: 20
  • Mon, Feb 6 2012 10:56 PM

    Re: RE: RE: Cadence noise aware PLL design flow: have lock problem Reply
    The point is that to get detailed help on this, you would be best logging a service request rather than covering it in the forum. The number of folks who will have got access to the workshop library is fairly small, so if you're expecting help from one of us here at Cadence, and we are having to reference information within that workshop (which contains some IP, hence the restrictions on access), it's best not to do so in a public forum. Plus the fact that it's not obvious why it is not working for you and would need some more detailed investigation.

    BTW, my guess with the merged paragraphs is that you're using Chrome; Chrome does not seem to work well with the community forums.

    Andrew
    • Post Points: 20
  • Tue, Feb 7 2012 11:00 AM

    • lunren
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    Re: RE: RE: Cadence noise aware PLL design flow: have lock problem Reply

     Hey Andrew,

     Thanks a lot for your reply. First of all, I use apple Mac which might be the reason that it merges paragraphes. I will try to submit a service request. Here are two more questions:

    1) What's the flow to submit such a service request?

    2)  Do we still need special license to run PLL Macro Model Wizard even we have mmsim101?

     Regards,

     Lunren

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    • Post Points: 20
  • Tue, Feb 7 2012 2:12 PM

    • Tawna
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    RE: RE: RE: Cadence noise aware PLL design flow: have lock problem Reply
    Hi Lunren,
     
    To log a Service Request, go to http://support.cadence.com
    To access Cadence Online Support, you need to be a Cadence customer on Maintenance.
    If you are a University student, then you'd need to find your Cadence contact within your University for login instructions.
     
    When you go to the website, there will be a section that says:
     
    Cadence Log In
     
    Cadence uses a single Login ID for all applications. You will use the same Login ID and password for each application you are registered with.
     
    (and a field for your email address and password and a login button).
     
    If you have not registered before, go to:
    ---------------------------------------
    New User?
    Don't have an account? Register Now
    A single Cadence account can be used to access numerous Cadence online resources. Access to certain sections of Cadence's website may be limited.
    Registration Help
    Having trouble with registration?
    Click on the
    Help link on the top right corner of the page to find answers to questions and typical problems you might face during the registration process.
     
    ---------------------------------------
     
     
    To obtain the PLL Noise Aware Flow library (that I mentioned in my previous email), you need to have the SPLA and Kit exhibit signed (also mentioned previously).  It is only that library (containing the IP) which is not available to the "general public".   It is easier to use the Noise Aware PLL Flow if you have access to that library.
     
     
    best regards,
     
    Tawna

    Best regards, Tawna Wilsey Staff Support AE, Global Customer Support Cadence Design Systems, Inc.
    • Post Points: 20
  • Tue, Feb 7 2012 3:40 PM

    • lunren
    • Top 500 Contributor
    • Joined on Thu, Oct 1 2009
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    Re: RE: RE: RE: Cadence noise aware PLL design flow: have lock problem Reply
    Hi Tawna and Andrew, I just submitted a SR with the simulation folds. You should be able to read all the log file and the netlist. Thanks, Lunren
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    • Post Points: 5
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Started by lunren at 06 Feb 2012 04:16 PM. Topic has 9 replies.