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 reg : vhdl design with systemverilog testbench 

Last post Thu, Jan 12 2012 1:38 AM by Srikanth Madam. 0 replies.
Started by Srikanth Madam 12 Jan 2012 01:38 AM. Topic has 0 replies and 2568 views
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  • Thu, Jan 12 2012 1:38 AM

    • Srikanth Madam
    • Not Ranked
    • Joined on Mon, Oct 17 2011
    • Hyderabad, Andhra Pradesh
    • Posts 4
    • Points 50
    reg : vhdl design with systemverilog testbench Reply

    Hi Everyone,

              Could someone help me in verifying "vhdl" design using systemverilog testbench , i am using INCISIVE 10.20.026 as "irun sample.vhd tb_sample.sv" and it is giving the following error

    " ASSERT/WARNING (time 0 FS) from package ieee.STD_LOGIC_ARITH, this builtin function called  from process tb.c1:$PROCESS_000 (architecture worklib.sample:behv)
    Built-in function result set to 'X' due to a ('U', 'X', 'W', 'Z', '-') in an operand."

        So anyone please help me in verifying the design

     

    Thanks in Advance

    With regards

    Srikanth M.

     

    • Post Points: 5
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Started by Srikanth Madam at 12 Jan 2012 01:38 AM. Topic has 0 replies.