SOC Encounter :: LEF File load Failed 

Hi

I am using SoC Encounter 10.1. While importing the design I load the netlist file (i.e. *.v file) and then add the LEF file to the list.

When I press OK then I get this error.

**ERROR: (ENCSYT-16013):
/sw/cadence/libraries/cmos065_522-2/CORL65LPSVT_5.1/CADENCE/LEF/
CORL65LPSVT_soc.lef failed

I am unable to resolve this issue.

Any suggestions ?

Thanks,

Qazi

 Hi Qazi,

 Can you explain more about how exactly you're loading the data? Are you using commands? The GUI? You should be using the Import Design form, which has specific fields for the verilog, LEFs, etc. Make sure you have a tech lef and that it's the first lef that gets read in.

- Kari

Hi

Ya Actually I am using GUI for importing design.

I added the netlist (*.v) file. Then I have to add the LEF file I only loaded one LEF file i.e. named like

/sw/cadence/libraries/cmos065_522-2/CORE65LPSVT_5.1/CADENCE/LEF/CORE65LPSVT_soc.lef

you mentioned the tech lef file.. Where could I find a tech lef file ?

Thanks,

Qazi

 I'm just guessing, but it seems like the LEF you're loading is just for a set of std cells. The "tech lef" is a lef file that has the layer and via definitions, spacing rules, etc. Sometimes it's part of the std cell lef, sometimes not. You can usually get it from the either the std cell vendor or from the foundry.

Thanks, I resolved the previous issue. 

 But now I am facing another problem. When I Import the design I get the pin size too large. How can I educe the size ??

Does it depend on LEF file or what ??

 Image is below.......

 Looks like you're also loading a floorplan file of some sort. Can you check that and see if the pin sizes are defined? I've never seen this, and these triangles are not actual pin shapes, just markers, so I'm not really sure how their size is controlled.

Hi,

I found the problem and resolved. Actually I was not using any Floorplanning while taking the pic that I shown before.

Now I am facing another problem. I am unable to route the design properly. After setting up the Floorplan the design when I place the Standard Cells it also routes the metals as well and the metals are overlapped. I am not sure why it does so and how could I overcome this issue.

I am attaching a pic of the layout as well.

Right after placing the design, it is possible that a trial route is also launched.

If true, then it is quite normal to have obvious violations such as overlapping wires.

Run a nanoroute on your design, this should give you a more correct routing (not always DRC free though, but your small design can't possibly have such problems, unless you set some really compelling blockages)

 I am unable tofigure out the problem. When I run the nanoRoute then I get an error and I am unable to get through this also 

 I get some Warnings and Errors,

#WARNING (NRDB-318) MINIMUMCUT rule specifying 1 (<= 1) cuts for LAYER M1 is ignored
#WARNING (NRDB-318) MINIMUMCUT rule specifying 1 (<= 1) cuts for LAYER M1 is ignored
#WARNING (NRDB-318) MINIMUMCUT rule specifying 1 (<= 1) cuts for LAYER M2 is ignored
#WARNING (NRDB-318) MINIMUMCUT rule specifying 1 (<= 1) cuts for LAYER M2 is ignored
#WARNING (NRDB-318) MINIMUMCUT rule specifying 1 (<= 1) cuts for LAYER M3 is ignored
#WARNING (EMS-27) Message (NRDB-318) has exceeded the current message display limit of 20.
#To increase the message display limit, refer to the product command reference manual.
#WARNING (NRDB-2005) SPECIAL_NET vdd has special wires but no definition for instance-pin connection. This will cause routability problems later.
#WARNING (NRDB-2005) SPECIAL_NET gnd has special wires but no definition for instance-pin connection. This will cause routability problems later.
#NanoRoute Version v10.10-p002 NR101202-1141/USR66-UB
#WARNING (NREX-28) The height of the first routing layer M1 is 0.000000. It should be larger than 0.000000
#WARNING (NREX-29) The metal thickness of routing layer M1 is 0.000000. It should be larger than 0.0. Add this to the technology information for better accuracy.
#WARNING (NREX-30) Please also check the height and metal thickness values for the routing layers heigher than routing layer M1
#WARNING (NREX-4) No Extended Cap Table was imported. Not enough process information was provided either and default Extended Cap Table database will be used.
#WARNING (NRDB-2040) Rule LEF_DEFAULT doesn't specify any vias that satisfy a minimum area rule on M2 M3 M4 M5 M6 M7
#WARNING (NRDB-778) No multicut vias are defined for LAYER M1 in RULE LEF_DEFAULT. When a LEF MINIMUMCUT rule is defined for a layer, you must define multicut vias for the layer in the LEF file. Edit your LEF file and read it in again.
#WARNING (NRDB-778) No multicut vias are defined for LAYER M2 in RULE LEF_DEFAULT. When a LEF MINIMUMCUT rule is defined for a layer, you must define multicut vias for the layer in the LEF file. Edit your LEF file and read it in again.
#WARNING (NRDB-778) No multicut vias are defined for LAYER M3 in RULE LEF_DEFAULT. When a LEF MINIMUMCUT rule is defined for a layer, you must define multicut vias for the layer in the LEF file. Edit your LEF file and read it in again.
#WARNING (NRDB-778) No multicut vias are defined for LAYER M4 in RULE LEF_DEFAULT. When a LEF MINIMUMCUT rule is defined for a layer, you must define multicut vias for the layer in the LEF file. Edit your LEF file and read it in again.
#WARNING (EMS-27) Message (NRDB-778) has exceeded the current message display limit of 20.
#To increase the message display limit, refer to the product command reference manual.
#WARNING (NRDB-2040) Rule virtuosoDefaultSetup doesn't specify any vias that satisfy a minimum area rule on M2 M3 M4 M6
# M1           H   Track-Pitch = 10.000    Line-2-Via Pitch = 0.180
# M2           V   Track-Pitch = 10.000    Line-2-Via Pitch = 0.200
# M3           H   Track-Pitch = 10.000    Line-2-Via Pitch = 0.200
# M4           V   Track-Pitch = 10.000    Line-2-Via Pitch = 0.200
# M5           H   Track-Pitch = 10.000    Line-2-Via Pitch = 0.200
# M6           V   Track-Pitch = 10.000    Line-2-Via Pitch = 0.800
# M7           H   Track-Pitch = 10.000    Line-2-Via Pitch = 0.800
# AP           V   Track-Pitch = 10.000    Line-2-Via Pitch = 5.000
#ERROR (NRDB-158) There is no default via from LAYER M1 to LAYER M2 in RULE LEF_DEFAULT.
#Cpu time = 00:00:01
#Elapsed time = 00:00:01
#Increased memory = 1.00 (Mb)
#Total memory = 308.00 (Mb)
#Peak memory = 342.00 (Mb)
#WARNING (NRIF-19) Fail to complete globalDetailRoute on Tue Feb 14 14:30:07 2012

How can I resolve this issue ????

 Apparently it is still a tech lef problem, because, for example:

"#WARNING (NREX-28) The height of the first routing layer M1 is 0.000000. It should be larger than 0.000000"

shows that either your tech lef file is badly defined, or that encounter is using a default value.

 As stated by Kari previously, this type of information (layer height, spacing, via rules, etc...) is defined in the technology .lef file. To be sure you have such information, just open the.lef files you are using and search for layers definitions looking like that:

LAYER M1

   TYPE ROUTING;

   DIRECTION HORIZONTAL;

   PITCH 0.4;

   HEIGHT 1.32;

   THICKNESS 0.42;

   ...

END M1

 If none of the .lef files you are using have such definitions, then you are still missing something. I would advise you to dig a bit into the directory in which you have your technology/library files to find it.

 Also, it may be the order of your lef files that is not correct. In the Import Design form, the correct order is to specify first the tech .lef file, then the stdcell .lef file (if in a separate file), then the block .lef files.

 If everything else fail, then go back to step 1: ask your vendor/foundry to provide you this tech .lef.

I checked the LEF files and I think the layers are defined properly. One of the layer definition is 

LAYER M1
  TYPE ROUTING ;
  DIRECTION HORIZONTAL ;
  PITCH 10 10  ;
  WIDTH 0.09 ;
  AREA 0.042 ;
  SPACINGTABLE

 ....

END M1

But still I can't get throught the error that I mentioned earlier. 

When I finish the floorplan I am unable see the blocks that supposed to be appear around the floorplan area. 

 I am attaching the figure please suggest if something is possible ....

 There are no site rows in your design (and also, what are the blocks you say are missing? standard cells? power rings?)

  I still find your tech lef strange. If for example the unit defined is the micron, we see that you have a routing grid with a distance between the routing tracks (defined by the PITCH statement) of 10 microns, even though the default routing width (WIDTH statement) is 0.09 microns. The width can be more of course, but my point is that it seems illogical to allow a so small width with a distance a hundred times more important.