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 how to pass array of parameters through CDF down to a verilogA code? 

Last post Mon, Dec 16 2013 2:57 AM by Andrew Beckett. 6 replies.
Started by naderi 17 Nov 2011 08:36 AM. Topic has 6 replies and 4936 views
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  • Thu, Nov 17 2011 8:36 AM

    • naderi
    • Top 200 Contributor
    • Joined on Thu, Jul 31 2008
    • Posts 41
    • Points 625
    how to pass array of parameters through CDF down to a verilogA code? Reply

     Hello all,

     Is there any way to pass an array of parameters down to a verilogA code?

    if I put following statement in a verilogA sub-circuit.

    parameter real vdc[3:0] ={0,0,1,0};

    Then {0, 0, 1, 0} appears in CDF parameters for vdc. However, spectre complains later during circuit read-in.The error message is :

     Error found by spectre during circuit read-in.
        ERROR (SFE-874): "input.scs" 1087: Unexpected block statement "{".

    I realized if I enter the parameters within double-qoute as "{0, 0, 1, 0}" at CDF, then spectre will be happy and goes for simulation, but the results are incorrect.

     

    I wonder if there is any solution?

    Thanks,

    Ali

    • Post Points: 20
  • Wed, Dec 7 2011 10:31 PM

    Re: how to pass array of parameters through CDF down to a verilogA code? Reply

    Ali,

    Make the value in the CDF "[0 0 1 0]". It needs to be netlisted with spectre's vector syntax, rather than the VerilogA vector syntax.

    I just tried this, and it works fine.

    Andrew.

    • Post Points: 20
  • Thu, Dec 8 2011 9:37 AM

    • naderi
    • Top 200 Contributor
    • Joined on Thu, Jul 31 2008
    • Posts 41
    • Points 625
    Re: how to pass array of parameters through CDF down to a verilogA code? Reply

     Hi Andrew,

    Thanks for reply.

    Here is my verilogA code. When I enter "[0 0 1 0]" (as you sugessted) spectre complains about the missing comma between values.

    Giving  "[0, 0, 1, 0]" passes the compiler and then transient simulation shows wrong values for the output voltages as [ 589.3E6,  9.223E-297, 0.0, 0.0] .

    I tried it on IC6.1.4-64b.500.9 ,"v2009.4_23.21"

    Regards,

    Ali

    `include "constants.vams"
    `include "disciplines.vams"
    `define LENGTH 4

    module vbus(A);
    output [`LENGTH-1:0] A;
    voltage [`LENGTH-1:0] A;

    parameter real vdc[`LENGTH-1:0] =[0, 0, 0, 0];

    analog
    begin
            generate i (`LENGTH-1,0)
            begin
                    V(A[i]) <+ vdc[i] ;
            end
    end

    endmodule

     

    • Post Points: 20
  • Thu, Dec 8 2011 9:43 AM

    Re: how to pass array of parameters through CDF down to a verilogA code? Reply

    Ali,

    You misunderstood. The VerilogA code needs to use {0,0,1,0} syntax, but in the CDF you'll need to define the default as [0 0 1 0] (no commas, although commas are tolerated at the moment - but you get a warning about them not being supported in the future). Also, when you instantiate the block, with a different value, you'd need to specify it with square brackets. To illustrate what I mean, here's some VerilogA:

     `include "disciplines.vams"

    module blah (op,ip);

    output op;
    input ip;
    electrical op,ip;

    parameter real vdc[3:0]={0,0,1,0};

    analog begin

       V(op) <+ vdc[2]*V(ip);

    end

    endmodule

    and here's the corresponding spectre netlist:

     //

    I1 (o1 i1) blah vdc=[2 2 2 2]

    v1 (i1 0) vsource type=sine freq=1M ampl=1

    ahdl_include "blah.va"
    tran tran stop=2u

     

    • Post Points: 35
  • Thu, Dec 8 2011 11:00 AM

    • naderi
    • Top 200 Contributor
    • Joined on Thu, Jul 31 2008
    • Posts 41
    • Points 625
    Re: how to pass array of parameters through CDF down to a verilogA code? Reply

     Awesome, Worked just fine.

    Thanks,

    Ali

    • Post Points: 5
  • Tue, Oct 8 2013 4:55 PM

    • kawan
    • Not Ranked
    • Joined on Wed, Jun 26 2013
    • Posts 14
    • Points 205
    Re: how to pass array of parameters through CDF down to a verilogA code? Reply

     Andrew,

    I ran into the same problem and I tried out your solution. It did not work and I wonder if the solution is now different with cadence 6.1.5 ?

     // VerilogA for zakir_sim1, bb_prereg_ldo, veriloga

    `include "constants.vams"
    `include "disciplines.vams"

    module trim3bits(sel);
    output [2:0] sel;
    electrical [2:0] sel;

    parameter real trim[2:0] ={0,0,0};

    analog begin

    V(sel[2]) <+ trim[2]*1.1;
    V(sel[1]) <+ trim[1]*1.1;
    V(sel[0]) <+ trim[0]*1.1;

    end

    endmodule p, li { white-space: pre-wrap; }

    Begin Incremental Netlisting Oct 8 16:44:23 2013

    "ERROR (OSSHNL-524): Netlisting failed as function hnlNetNameOnTerm was called with a non-existent terminal name on current instance 'I6' in design 'zakir_sim1/test1/schematic'. Ensure that argument to this function is a valid terminal name and netlist again.\n\n"

    "ERROR (OSSHNL-524): Netlisting failed as function hnlNetNameOnTerm was called with a non-existent terminal name on current instance 'I6' in design 'zakir_sim1/test1/schematic'. Ensure that argument to this function is a valid terminal name and netlist again.\n\n"

    "ERROR (OSSHNL-524): Netlisting failed as function hnlNetNameOnTerm was called with a non-existent terminal name on current instance 'I6' in design 'zakir_sim1/test1/schematic'. Ensure that argument to this function is a valid terminal name and netlist again.\n\n"

    "ERROR (OSSHNL-524): Netlisting failed as function hnlNetNameOnTerm was called with a non-existent terminal name on current instance 'I6' in design 'zakir_sim1/test1/schematic'. Ensure that argument to this function is a valid terminal name and netlist again.\n\n"

    "ERROR (OSSHNL-524): Netlisting failed as function hnlNetNameOnTerm was called with a non-existent terminal name on current instance 'I6' in design 'zakir_sim1/test1/schematic'. Ensure that argument to this function is a valid terminal name and netlist again.\n\n"

    End netlisting Oct 8 16:44:23 2013

    ERROR (OSSHNL-514): Netlisting failed due to errors reported before. Netlist may be corrupt or may not be produced at all. Fix reported errors and netlist again.

    ...unsuccessful.

    • Post Points: 20
  • Mon, Dec 16 2013 2:57 AM

    Re: how to pass array of parameters through CDF down to a verilogA code? Reply

    That looks as if there's a mismatch between the pins on the symbol and the pins on the veriloga view. Or there's something wrong with the CDF.

    Andrew.

    • Post Points: 5
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Started by naderi at 17 Nov 2011 08:36 AM. Topic has 6 replies.