I hope you all are doing fine. I need some guidance regarding post-layout simulation of black-box digital cells from Artisan Standard Cell Library using Ultrasim. We have the verilog, lef and tlf files in the PDK along with CDB symbol database that we converted to OA database. We have imported verilog view in the library and therefore we have the symbol, cmos-sch and the functional views.
For example, I have done the automated layout and P&R using Encounter for two inverters in series. I have imported the gate-level netlist and the gds file in Virtuoso and have been able to succesfully perform DRC and LVS (using the black-box cells parameter for the LVS). The pre-layout (post-synthesis) simulations have also been successful using the Hierarchy Editor, changing the Standard-Cell's view to functional and using Spectre-Verilog or Ultra-Sim from inside the ADE.
However, when we create the av_extracted view, since the inverters cells are black-box, they are not present in the extracted netlist. When we create a dspf file from RCX extraction, the cell instance is there. But we run into following issues:
1. What is the method of using a dspf file through hierarchy editor? When we specify it as a source file there, it is not able to see through the hierarchy and find the embedded inverter cell instances.
2. Are we supposed to simulated the dspf in UltraSim through command-line? From here, UltraSim looks for subckt definition of inverter cell, which we do not have. Since the DSPF already has all the interconnect parasitics, we believe connecting a functional instance in that netlist would also suffice. But how to include the Verilog cell definition while using UltraSim through command-line?
Thanks and best regards,