Home > Community > Forums > Custom IC Design > Complex wire labels with iterated instances

Email

* Required Fields

Recipients email * (separate multiple addresses with commas)

Your name *

Your email *

Message *

Contact Us

* Required Fields
First Name *

Last Name *

Email *

Company / Institution *

Comments: *

 Complex wire labels with iterated instances 

Last post Thu, Oct 13 2011 4:56 AM by mtpank. 1 replies.
Started by mtpank 27 Sep 2011 01:52 AM. Topic has 1 replies and 1767 views
Page 1 of 1 (2 items)
Sort Posts:
  • Tue, Sep 27 2011 1:52 AM

    • mtpank
    • Not Ranked
    • Joined on Tue, Sep 27 2011
    • Posts 2
    • Points 10
    Complex wire labels with iterated instances Reply

    Hi all,
    I'm working with the CIW version 5.10.41 and came across with the following problem when doing schematics (Virtuoso schematic composer) for a full custom mixed signal design:

    Let's assume that I have a 3 bit bus going into an instance (I), and I need 8 of these instances all together. These instances should be hooked up with binary weighted signals. So the top level would be something like this:
    pin a<2:0>
    pin b<2:0>

    I<0:7> connected with a wire labeled (expanded form): a<2>,a<1>,a<0>,a<2>,a<1>,b<0>,a<2>,b<1>,a<0>,a<2>,b<1>,b<0>,b<2>,a<1>,a<0>,b<2>,a<1>,b<0>,b<2>,b<1>,a<0>,b<2>,b<1>,b<0>

    so that the incoming 3 bit bus is different for each instance and can not be simply labeled with a<(2:0)*4> or similar compact expression. I don't have access to standard cell library with this specific DK, so vhdl code + synthesis is out of question. I can compress the string above a little bit e.g. a<2:0>,a<2:1>,b<0>,.... b<2:0>, but it's not helping very much when extending the concept from 3 bits to 10 bits. Notice, that only the prefix changes, the index is the same 3 bit pattern (2:0) for each instance.  I was wondering if it would be possible to take the instance index as an input argument and perform a decimal to binary conversion for it and finally substitute all zeros with prefix a and all ones with prefix b. However, I don't know how this should be implemented in practice.

    patchcords?
    skill script?
    embedded verilog module?

    Filed under: ,
    • Post Points: 5
  • Thu, Oct 13 2011 4:56 AM

    • mtpank
    • Not Ranked
    • Joined on Tue, Sep 27 2011
    • Posts 2
    • Points 10
    Re: Complex wire labels with iterated instances Reply

    Answering to my own question...

    I wrote a few lines of matlab code that generates the desired wire labels to separate text files. Then I copy pasted these to appropriate places and got the job done. Maybe not very elegant solution but worked fine for me. It was afraid that Virtuoso does not support that long wire labels but it does - What a relief.

    • Post Points: 5
Page 1 of 1 (2 items)
Sort Posts:
Started by mtpank at 27 Sep 2011 01:52 AM. Topic has 1 replies.