I'm having problems with vias, which are exportet to GDS files.
I exportet the chip layout from Encounter to a GDS file:
streamOut chip.gds.gz -mapFile ../setup/gds2.map -libName DesignLib -stripes 1 -units 1000 -mode ALL
The GDS file is hierarchical and instanciates standard cells, io pad cells and vias, but does not define them, because Encounter only has the coarse definitions from the LEF files. Thats fine, because they will be used from Virtuoso.
Then I've imported this GDS file into ICFB:
CIW: File -> Import -> Stream...
Input File: /home/glaser/chip/routing/run/chip.gds.gz
Top Cell Name: chip
Output Library Name: iac2010
Retain Reference Library (No Merge) [X]
Do Not Overwrite Existing Cell [X]
Everything works fine, because the referenced standard cells are now taken from the according library in the library manager. When I open the layout, all cells and vias are shown properly.
When the layout is exported from ICFB again, the "Individual Cell Statistics" complains
(VIA2_C$$175108140/layout) -- (referenced, but not defined, no data created).
(VIA3_C$$175104044/layout) -- (referenced, but not defined, no data created).
(VIA1_C$$175100972/layout) -- (referenced, but not defined, no data created).
When loading the GDS file with "calibredrv", I get similar messages:
WARNING: Cell VIA1_C$$175100972 is referenced but not defined. Empty cell used.
WARNING: Cell VIA2_C$$175108140 is referenced but not defined. Empty cell used.
WARNING: Cell VIA3_C$$175104044 is referenced but not defined. Empty cell used.
When I zoom in at places with lots of wires, no vias are shown.
My analysis has shown, that the GDS file exported by Encounter uses for the three via types (4 metal process) instances from the technology library. The via cells are called VIA1_C, VIA2_C and VIA3_C. The layout shown by Virtuoso shows lots of instances of these vias.
All these vias are PCells for which the parameters yBias, xBias, yPitch, xPitch, column, row, l, and w can be modified.
When exporting the layout, for every parameter combination a unique definition with a unique name is created (therefore the suffix '$$123456789', which number changes every time of export). Fortunately there is only one combination of parameters for each via type.
In the exported GDS file, the vias are instanciated with the suffix (e.g. 'VIA1_C$$175100972'). The cell definition OTOH are embedded without the suffix (e.g. 'VIA1_C').
I've tried all combinations of options of the export dialog, but none has helped.
I've also done an additional test: I've drawn a layout by myself in Virtuoso (without import) with paths and vias (Create -> Path, draw a line, then press [F3] and choose another layer). When then editing the via instance properties ([q] key), the option "Parameter" is deactivated. OTOH when I instanciate a via directly from the technology library, then this option is enabled and all the parameters mentioned above can be edited. When this layout is then exported to a GDS file, all vias get their own suffix (different ones for automatically and manually instanciated). The via cell definition as well as the via instances use the suffix correctly. So for layouts drawn completely in Virtuoso, everything works ok.
For the imported layout, all vias have the "Parameter" option enabled and proper values are set. When exported, the instances get a suffix, but the cell definitions do not. This is why they are wrongly referenced.
Could you please help me find and solve the problem?
I'm using a 350nm process with 4 metal layers, Cadence First Encounter v08.10-s273_1 und Cadence Virtuoso 220.127.116.110.6.143.