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 Forcing a VHDL signal from a Verilog Test/Env 

Last post Fri, Aug 31 2012 5:42 AM by ravisguptaji. 4 replies.
Started by ashfaqh 21 Jul 2011 10:48 PM. Topic has 4 replies and 5147 views
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  • Thu, Jul 21 2011 10:48 PM

    • ashfaqh
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    Forcing a VHDL signal from a Verilog Test/Env Reply

     I have a Testbench with a DUT which has VHDL and Verilog RTL modules.  The tb_top is verilog.  The test file is a verilog.  

     From the verilog test, I need to force a signal inside the DUT several hierarchies down.

     The signal I need to force is inside a VHDL module.   This signal is not available at the top level.

     How do I do it?

     I am using ncverilog/ncvhdl/irun version of 9.2.

     Any suggestions with some simple code example is going to be very helpful. 

     Thanks, 

     -Ashfaq Hossain 

    • Post Points: 35
  • Fri, Jul 22 2011 4:45 PM

    • Mickey
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    Re: Forcing a VHDL signal from a Verilog Test/Env Reply

    Hi Ashfaq,

    You need to use $nc_force to force a vhdl down in the design hierarchy from a verilog testbench.  It's fairly simple.   


    $nc_force ("source", "value", "after_time", "rel_time", "repeat_time",  "cancel_time", "verbose");

    for example,
    $nc_force (path.to.r1, "'1'", "verbose");

    above example will force a '1' value (note that vhdl notation is used for the value to be assigned, if the destination was verilog you would use 1'b1) onto the hierarchical location, path.to.r1.  Additionally verbose is included to have the tools output a message to stdout when the code is encountered during simulation.

    If you would like more information regarding the other options, go to support.cadence.com and do a search using $nc_force as the search term. 

    Best regards,
    Mickey

    • Post Points: 20
  • Sat, Jul 23 2011 9:14 AM

    • ashfaqh
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    Re: Forcing a VHDL signal from a Verilog Test/Env Reply

    Mickey:

     Thanks for your response.  I tried and got the following error msg.  Please suggest.

     Thanks,

     -Ashfaq

     

     Top level design units:
                    $unit_0x22e511b2
                    tb_test
              $nc_force(tb_test.u_tb_controller.u_hier1_top.hier2.hier3.hier4.hier5.signal_name[3], "'1'", "verbose") ;
                                                                                                                                                 |
    ncelab: *E,CUIOCP (./testbench/tb_test.v,109|141): Out-of-module reference terminating in a VHDL scope is not allowed (tb_test.u_tb_controller.u_hier1_top.hier2.hier3.hier4.hier5.signal_name[3]).
    ncelab: Memory Usage - 20.8M program + 170.3M data = 191.1M total
    ncelab: CPU Usage - 0.2s system + 1.2s user = 1.4s total (3.6s, 38.2% cpu)
    irun: *E,ELBERR: Error during elaboration (status 1), exiting.

    • Post Points: 5
  • Mon, Jul 25 2011 6:49 AM

    • tpylant
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    RE: Forcing a VHDL signal from a Verilog Test/Env Reply
    It looks like you did not put quotes around the signal name.  All the arguments need to be strings:

    $nc_force ("source", "value", "after_time", "rel_time", "repeat_time",  "cancel_time", "verbose");

    Tim
    • Post Points: 20
  • Fri, Aug 31 2012 5:42 AM

    • ravisguptaji
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    Re: RE: Forcing a VHDL signal from a Verilog Test/Env Reply

    Hi,

    I was able to source to the signal of interest, but i have a requirement to keep giving different values to that signal of interest.

    I tried something like this, which din't work out.

    repeat(4) begin

    $nc_force("source", "reg") ;

    reg = reg+1'b1;

    end

    The reg value in my simulation keeps incrementing but the source signal of interest does not increment.

    Is there any other way to perform the same kind of operation??

    Regards,

    Ravi

    • Post Points: 5
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Started by ashfaqh at 21 Jul 2011 10:48 PM. Topic has 4 replies.