You need to use $nc_force to force a vhdl down in the design hierarchy from a verilog testbench. It's fairly simple.
$nc_force ("source", "value", "after_time", "rel_time", "repeat_time", "cancel_time", "verbose");
$nc_force (path.to.r1, "'1'", "verbose");
above example will force a '1' value (note that vhdl notation is used for the value to be assigned, if the destination was verilog you would use 1'b1) onto the hierarchical location, path.to.r1. Additionally verbose is included to have the tools output a message to stdout when the code is encountered during simulation.
If you would like more information regarding the other options, go to support.cadence.com and do a search using $nc_force as the search term.