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 IBM45nm (SOI ) technology Gate resistance problem 

Last post Mon, Jul 18 2011 9:44 AM by nadroit. 0 replies.
Started by nadroit 18 Jul 2011 09:44 AM. Topic has 0 replies and 2015 views
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  • Mon, Jul 18 2011 9:44 AM

    • nadroit
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    • Joined on Tue, Jul 12 2011
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    IBM45nm (SOI ) technology Gate resistance problem Reply

    Hi All

     I am using IBM45nm (SOI) technology provided by MOSIS for designing RF circuits. I used cadence 6.1 to carry out some simulations. When I do typical DC simulation and print the oprating points I do not see the value for gate resistance . Why is this happning? is there no gate resistance in SOI technology? (I checked the BSIMSOI manual and they do model gate resistance and ther RF parameters) I bit confused please help.

    Thanks 

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Started by nadroit at 18 Jul 2011 09:44 AM. Topic has 0 replies.