I have been using mixed signal simulation to test a SRAM design and it works great. I have a Verilog-AMS testbench driving the inputs and validating the outputs, and use the AMS simulator with Ultrasim as the solver and OSS as the netlister.
My problem is that I would like to use this same setup to run the same simulation on the extracted netlist. I have tried Spice Import, but the netlist is huge (1 GB) so I killed it after two days. Is there any way to just point Cadence to the netlist and tell it to use that? I have tried various things but never had any success. Or alternatively, is there a way to "export" the AMS run then manually hack the files to include the right netlist?
FYI, I am using StarRCXT which exports to Spice format now. I have been able to use Ultrasim to simulate the extracted netlist manually, but cannot integrate it into the AMS flow.