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 *Fence* *SRC* *MME* Buffers in Clock Tree 

Last post Tue, Jun 28 2011 9:44 AM by Nataraja G. 2 replies.
Started by Nataraja G 27 Jun 2011 09:31 AM. Topic has 2 replies and 1540 views
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  • Mon, Jun 27 2011 9:31 AM

    • Nataraja G
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    • Joined on Sun, Jun 20 2010
    • Hyderabad, Andhra Pradesh
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    *Fence* *SRC* *MME* Buffers in Clock Tree Reply

    With 10.11USR1 enconter  we are seeing new type of buffers being added at CTS

    *MMExc__L1_I0 these kind of naming convention was given if a pin was declared excludedPin in clock spec file

    but in 10.1 *MMExc*  buffers are being added without specfying excludedPin and this is not because of  loops in clock path ( obviosuly with ckSynthesis -breakloop we are expected to see excluded buffer at loop backs )

    I have never seen Insance names with *Fence* and *SRC*   in clock path 

     What do they signify ? i have searched fetxtref and socUG for these things but havn't found anything 

     

    hope i am clear ,

     

    Thanks

     Nataraja

    its good to be back :)

     

    -Nataraja G
    • Post Points: 20
  • Tue, Jun 28 2011 7:08 AM

    • Kari
    • Top 10 Contributor
    • Joined on Tue, Jul 15 2008
    • Cary, NC
    • Posts 693
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    Re: *Fence* *SRC* *MME* Buffers in Clock Tree Reply

     Welcome back!

    I think SRC has to do with balancing to an output port, and Fence could be due to power domains or setCTSMode -honorFence, or maybe some other things. Do any of these make sense for your design?

     

     

    • Post Points: 20
  • Tue, Jun 28 2011 9:44 AM

    • Nataraja G
    • Not Ranked
    • Joined on Sun, Jun 20 2010
    • Hyderabad, Andhra Pradesh
    • Posts 16
    • Points 360
    Re: *Fence* *SRC* *MME* Buffers in Clock Tree Reply

     we have set this,

     setCTSMode -honorFence false

     still fence buffer's are added and we dont have power domains in the design

     

    Fence buffers are being added to preserve a module port , in SDC file we have generated clock definitions at these ports 

    So ckSynthesis is automatically preserving them ( though i havn't specified them in clock spec file ) ,

    while i was browing in schematic viewer i found this  common to all generated clock's 

     

    i dont think SRC is for balancing Output ports , tool uses CASACDE buffer's if that is the case 

     

    Regards 

    Nataraja

     

     

     

     

    -Nataraja G
    • Post Points: 5
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Started by Nataraja G at 27 Jun 2011 09:31 AM. Topic has 2 replies.