Thanks for your kindly reply. I know top-down is better. I just want to know how to do bottom-up synthesis.
My question is as following:
read the whole design for one time and then use like DC's set current_design, set_dont_touch, etc. to synthesis each submodules and then synthesis the top module. For this usage we only need invoke RC license for one time; if we read one submodule, and use RC to synthesis; then read another submodule to synthesis, etc. This will invoke RC license for many times. If the license is not enough, it may be not suitable.
So I want to know whether RC support this usage (like DC to read the whole large design for one time and then synthesis each submodules/top modules with bottom-up method) or not.