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 RTL compiler: how to do bottom-up synthesis 

Last post Tue, Jul 5 2011 11:51 PM by airland. 4 replies.
Started by airland 22 Jun 2011 04:24 AM. Topic has 4 replies.
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  • Wed, Jun 22 2011 4:24 AM

    • airland
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    • Joined on Wed, Jun 22 2011
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    • Points 65
    RTL compiler: how to do bottom-up synthesis Reply

    I used Design Compiler before and do synthesis bottom-up. Now I changed to use RTL compiler to do synthesis. I have read the user manual but I did not found how to do bottom-up synthesis using RTL compiler. Could any one tell me or show me a simple synthesis script for bottom-up synthesis?

    Thanks.

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    • Post Points: 20

  • Wed, Jun 22 2011 2:49 PM

    • croy
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    Re: RTL compiler: how to do bottom-up synthesis Reply

    Hi

     

    Do you have to stick to bottom-up? From what I understand DC users do bottom-up because of capacity limitations. You should find the capacity to be higher in RC, probably allowing you to switch to top-down.

     

    Chrystian

     
    • Post Points: 20

  • Wed, Jun 22 2011 10:17 PM

    • airland
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    Re: RTL compiler: how to do bottom-up synthesis Reply
    Yes, as our design is complex and clock is fast. Bottom-up may have better result

    I want to how to do bottom-up synthesis using RC.

    Could you please give some suggestions?

    Thanks very much!
    • Post Points: 20

  • Mon, Jun 27 2011 7:11 PM

    • grasshopper
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    • Chelmsford, MA
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    Re: RTL compiler: how to do bottom-up synthesis Reply

    Hi airland,

    not sure what you are after. Synthesis tools do not know what you are gonig to do with the netlist so you can always use a synthesized netlist at the next level up. What are the specific of your bottom-up question ? For fast designs I would argue that Top-down traditionally yields better results. The benefits of top-down are various:

    - single scripts environment to maintain

    - no need to budget/guesstimate I/O delays

    - better optimization of constant driven paths

    This is not to say there are no benefits to running bottom up but the motivation you mention is better suited for top-down than bottom-up IMHO. In anycase, as per your original question, please clarify what aspects you are looking for and we can try to better help you

     regards,

    gh-

     
    • Post Points: 20

  • Tue, Jul 5 2011 11:51 PM

    • airland
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    • Joined on Wed, Jun 22 2011
    • Posts 4
    • Points 65
    Re: RTL compiler: how to do bottom-up synthesis Reply

    Thanks for your kindly reply. I know top-down is better. I just want to know how to do bottom-up synthesis.

    My question is as following:

    read the whole design for one time and then use like DC's set current_design, set_dont_touch, etc. to synthesis each submodules and then synthesis the top module. For this usage we only need invoke RC license for one time; if we read one submodule, and use RC to synthesis; then read another submodule to synthesis, etc. This will invoke RC license for many times. If the license is not enough, it may be not suitable.

     So I want to know whether RC support this usage (like DC to read the whole large design for one time and then synthesis each submodules/top modules with bottom-up method) or not.

    Thanks.
    • Post Points: 5
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Started by airland at 22 Jun 2011 04:24 AM. Topic has 4 replies.