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 spare logic is not tied up/down properly after ECO route 

Last post Wed, Jul 20 2011 8:23 AM by J2mh. 1 replies.
Started by achilles 17 Jun 2011 11:26 AM. Topic has 1 replies and 1380 views
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  • Fri, Jun 17 2011 11:26 AM

    • achilles
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    • Joined on Thu, Jul 17 2008
    • Posts 4
    • Points 95
    spare logic is not tied up/down properly after ECO route Reply

    In my ECO step, a number of logic gates are freed up and become spare gates.  They should be connected to VDD or GND selectively.  What command should I use?  The large majority are grounded, but a few are tied high.

    Note: 

     I don't have tieHi or tieLo cells in my library; I want to hook up directly. 

    When I query the pin, the net shown is "NIL".

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    • Post Points: 20
  • Wed, Jul 20 2011 8:23 AM

    • J2mh
    • Not Ranked
    • Joined on Fri, Jun 25 2010
    • Sevilla, Sevilla
    • Posts 8
    • Points 60
    Re: spare logic is not tied up/down properly after ECO route Reply
    Hi,

    If your library have an inversor cell then you can create tiehigh and tielow cells, easily.

    Regards.
    • Post Points: 5
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Started by achilles at 17 Jun 2011 11:26 AM. Topic has 1 replies.