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 Layout of Enclosed Gate Transistors (EGTs or ELTs) 

Last post Tue, Jul 5 2011 11:42 AM by bnugent. 2 replies.
Started by bnugent 15 Jun 2011 04:47 AM. Topic has 2 replies and 1694 views
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  • Wed, Jun 15 2011 4:47 AM

    • bnugent
    • Top 500 Contributor
    • Joined on Thu, Jun 9 2011
    • Cambridge, MA
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    Layout of Enclosed Gate Transistors (EGTs or ELTs) Reply

     Hello,

     I'm designing an enclosed layout transistor but can not pass both DRC and LVS.

    I'm running IBM's PDK cmrf7sf V1.8.0.6 ML, out of virtuoso rev 6.1.4, and my simulator is Assura.

    Does anyone have any experience in getting a ELT to pass DRC and LVS in this process? Any help would be greatly appreciated

     

    Brian

    • Post Points: 20
  • Tue, Jul 5 2011 7:15 AM

    • Quek
    • Top 10 Contributor
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    Re: Layout of Enclosed Gate Transistors (EGTs or ELTs) Reply

    Hi Brian

    Hope that you do not mind the following the following minor correction:

    "my simulator is Assura" -> "my verification tool is Assura". : )

    Actually it would be best to contact your local Cadence support for this issue as I think a proper testcase is needed for the troubleshooting. If you have any difficulty in get official Cadence support, please upload the following files in the Assura run directory:

    yourDesign.cls
    yourDesign.log
    yourDesign.erc
    yourDesign.cfr (if it exists)

    Thanks
    Quek

    • Post Points: 20
  • Tue, Jul 5 2011 11:42 AM

    • bnugent
    • Top 500 Contributor
    • Joined on Thu, Jun 9 2011
    • Cambridge, MA
    • Posts 20
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    Re: Layout of Enclosed Gate Transistors (EGTs or ELTs) Reply
    Quek, Thanks for the tip! Brian
    • Post Points: 5
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Started by bnugent at 15 Jun 2011 04:47 AM. Topic has 2 replies.