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 Error when combining AXI UVC and AHB UVC 

Last post Wed, May 25 2011 3:08 AM by Louis Gao. 2 replies.
Started by Louis Gao 25 May 2011 01:14 AM. Topic has 2 replies and 2094 views
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  • Wed, May 25 2011 1:14 AM

    • Louis Gao
    • Not Ranked
    • Joined on Wed, Mar 30 2011
    • Posts 3
    • Points 30
    Error when combining AXI UVC and AHB UVC Reply

    My testbench need both AXI UVC and AHB UVC. I can successfully run each of them. But when I try to integrate both UVCs into one testbench. I got the following error mesage:

    irun: *N,OVMW: The use of the -ovm option will automatically suppress the following warnings
            PMBDVX
            BIGWIX
    .
    Compiling UVC core code. Please wait ....................
    Compiling vr_axi 09.20.003-s ...............
    Compiling vr_ahb 09.20.003-s
    Linking. This may take a few minutes ...............

    irun: *E,SNLDRN: A failure occurred while trying to generate internal simulation files using the dynamic specman library
    .....

            1 check was modified.
            1 check was modified.
            1 check was modified.
               *** Error: Items used with per_instance option must be gradable. line 1490
            in @vr_axi_coverage

    In my top module file, the "vr_axi_top.sv" and "vr_ahb_top.sv" are included.

    `include "vr_axi_top.sv"
    `include "vr_ahb_top.sv"

    module vr_amba_top_tb();
       import ovm_pkg::*;
     ...

    endmodule

    Here is the content of the UVC top file "vr_axi_top.sv":

    `ifndef OIG_VR_AXI_TOP
    `define OIG_VR_AXI_TOP

    // pragma oig_irun top_e_files = vr_axi/e/api/ovm/sv_generated_api/vr_axi_ovm.e
    // pragma oig_irun oig_params = -uvc_name vr_axi -version 08.20.002-s -eexp vr_axi/misc/vr_axi_cb_ovm.eexp -e_file vr_axi/e/api/ovm/vr_axi_ovm_top.e -base_name vr_axi

    `include "ovm_macros.svh"
    `ifndef OVM_MB_DEFINES_SVH
       `define SN_SV_MP_OVM_OPEN_SOURCE
    `endif

    `include "vr_axi_defines.sv"
    `include "vr_axi_dut_intf.svh"
    `include "vr_axi_extensions.svh"
    `include "vr_axi_classes.svh"

    `endif

    Here is the content of "vr_ahb_top.sv":

    `ifndef OIG_VR_AHB_TOP
    `define OIG_VR_AHB_TOP

    // pragma oig_irun top_e_files = vr_ahb/e/api/ovm/sv_generated_api/vr_ahb_ovm.e
    // pragma oig_irun oig_params = -uvc_name vr_ahb -version 08.20.002-s -eexp vr_ahb/misc/vr_ahb_cb_ovm.eexp -e_file vr_ahb/e/api/ovm/vr_ahb_ovm_top.e -base_name vr_ahb


    `include "ovm_macros.svh"
    `ifndef OVM_MB_DEFINES_SVH
       `define SN_SV_MP_OVM_OPEN_SOURCE
    `endif

    `include "vr_ahb_defines.sv"
    `include "vr_ahb_dut_intf.svh"
    `include "vr_ahb_extensions.svh"
    `include "vr_ahb_classes.svh"

    `endif

    I guess there might be some conflicts of the pragmas. Who can help me on this issue?

    Thanks very much in advance.

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    • Post Points: 20
  • Wed, May 25 2011 1:44 AM

    • StephenH
    • Top 25 Contributor
    • Joined on Tue, Sep 2 2008
    • Bristol, Avon
    • Posts 258
    • Points 4,100
    Re: Error when combining AXI UVC and AHB UVC Reply

    Hi Louis.

    I think it would be best if we put you in touch with your local verification AE at Cadence. If you don't already have a contact, please send me a private message with your company email address and I'll help find you the right person.

    At a first glance I think the problem might be related to your bus width definitions; I'm pretty certain that there is nothing wrong with the header files as other people have used these 2 VIPs together with no issue.

    If the ID or  strobe widths are very large, then the default coverage will not work as the ranges are too big.
    You can try setting "-defineall VR_AXI_LARGE_ID" and/or "-defineall VR_AXI_LARGE_STROBE" on your irun command line and see if that helps.

    Regards,
    Steve

    Steve Hobbs / Applications Engineer / Cadence Functional Verification
    Filed under: ,
    • Post Points: 20
  • Wed, May 25 2011 3:08 AM

    • Louis Gao
    • Not Ranked
    • Joined on Wed, Mar 30 2011
    • Posts 3
    • Points 30
    Re: Error when combining AXI UVC and AHB UVC Reply

    Hi Steve,

    You're correct. This problem is really related to the bus ID width VR_AXI_MAX_ID_WIDTH.

    The ID width of my design is 13-bit. So I set VR_AXI_MAX_ID_WIDTH=13. The large number resulted the failure. When I reduce it to VR_AXI_MAX_ID_WIDTH=4, my simulation works.

    But the  "-defineall VR_AXI_LARGE_ID" doesn't work for the VIP version I'm using 09.20.003.

    I plan to upgrade to 09.20.005 or higer version.

    Thank you very much.

    Louis

    • Post Points: 5
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Started by Louis Gao at 25 May 2011 01:14 AM. Topic has 2 replies.