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 Help for pnoise simulation in cadencespectre for VCO simulation 

Last post Sat, Nov 23 2013 8:56 AM by venkateshjutur. 2 replies.
Started by Analog Design 16 May 2011 01:54 AM. Topic has 2 replies and 6418 views
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  • Mon, May 16 2011 1:54 AM

    Help for pnoise simulation in cadencespectre for VCO simulation Reply


        When I am doing pnosie analysis in cadence spectre (IC 416) , the simulation prematuarly teminated & error flushing like below

    Provided I have fixed tstb =200ns for beat frequency = 10MHz

    pss has reached the maximum iterations (20).

    Error found by spectre during periodic steady state analysis `pss'.
            pss analysis did not converge. The last unconverged solution is saved.

    The following set of suggestions may help you avoid these convergence difficulties.

     1.  Carefully evaluate and resolve any notice, warning or error messages.

     2.  Providing a larger value for tstab generally improves convergence. While not always necessary, one occasionally needs set tstab to a value equal or greater than the time needed for the circuit to approximately reach steady state.

     3.  While trapezoidal rule ringing is annoying in transient analysis, in PSS analysis it can cause the shooting iteration to stall before convergence is achieved. This problem can be remedied by changing the method from traponly to either trap, gear2, or gear2only.

     4.  Increase the maximum iterations for shooting methods using the maxperiods parameter. Sometimes the analysis may need more than the default number of iterations to converge. However, there are situations that prevent convergence regardless of how many iterations are taken. In this case, increasing the iteration limit simply results in the simulator taking longer to fail.

     5.  If the shooting iteration approaches convergence and then stalls, it may be because the tolerance on the shooting method is too tight. In this case, try loosening steadyratio, which controls how close to steady-state the result must be before it is declared to be converged.

     6.  Finally, tightening the normal simulation tolerances (maxstep, reltol, lteratio, errpreset) can help resolve convergence problems in PSS. Avoid using errpreset=liberal.

    Analysis `pss' terminated prematurely due to error.

    Error found by spectre.
        PSS analysis must be executed before pnoise. Analysis skipped.

    Analysis `pnoise' terminated prematurely due to error.
    modelParameter: writing model parameter values to rawfile.
    element: writing instance parameter values to rawfile.
    outputParameter: writing output parameter values to rawfile.
    designParamVals: writing netlist parameters to rawfile.
    primitives: writing primitives to rawfile.
    subckts: writing subcircuits to rawfile.


    Can help someone regarding this issues. 



    • Post Points: 20
  • Mon, May 16 2011 12:59 PM

    • Tawna
    • Top 25 Contributor
    • Joined on Fri, Jul 11 2008
    • Snohomish, WA
    • Posts 216
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    Re: Help for pnoise simulation in cadencespectre for VCO simulation Reply



    This is actually a PSS convergence issue.  

    It is always helpful to include the subversion of software you are using when you post questions to the forum.  The command to obtain this is:     spectre -W

    Also, more details on the analysis and your circuit.   For example:

    - Are you using the shooting engine or harmonic balance?

    - Provide the analysis and options line from your netlist

    - Is this a digital (very sharp transitions) vco or more sinusoidal (or high Q) vco?


    You may want to look at the following Cadence Online Support solutions:  (you must be a Cadence customer.  University accounts must consult with their university-Cadence contact person.)





    best regards,



    Best regards, Tawna Wilsey Staff Support AE, Global Customer Support Cadence Design Systems, Inc.
    • Post Points: 20
  • Sat, Nov 23 2013 8:56 AM

    how to scale down inductor value for FINFET(25nm) where i have L value for 180nm Reply
    i am designing VCO circuit using 25nm tech FINFET
    i found VCO topology in one paper with W/L ratio of FETS and inductor value (2.4nH) for 180nm tech given in that paper
    my question is how to change the corresponding width for BSIMCMG FINFET where length is L=25nm
    and also how to scale inductor value for this FINFET tech   
    thanks in advance
    • Post Points: 5
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Started by Analog Design at 16 May 2011 01:54 AM. Topic has 2 replies.