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 Confused TechFile & Simulation 

Last post Tue, Jul 5 2011 8:05 AM by Quek. 1 replies.
Started by eactor 12 May 2011 04:16 AM. Topic has 1 replies and 1371 views
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  • Thu, May 12 2011 4:16 AM

    • eactor
    • Not Ranked
    • Joined on Thu, May 12 2011
    • Posts 1
    • Points 20
    Confused TechFile & Simulation Reply
    Hello,
    I designed my own transistor layout by coding a SKILL pcell. The next thing should be a own spectre modle, but the only thing I can do right now is:
    -create a schematic view for my layout which would include a transistor out of my techfile
    Normaly I thought I would connect some kind of spectre netlist, which includes my verilog modlue, to the Layout CellView, but maybe thats a totally wrong approach?
    cheers Paul

    ps hopefully not to messed up
    • Post Points: 20
  • Tue, Jul 5 2011 8:05 AM

    • Quek
    • Top 10 Contributor
    • Joined on Wed, Oct 14 2009
    • Singapore, 00-SG
    • Posts 1,051
    • Points 15,990
    Re: Confused TechFile & Simulation Reply

    Hi Paul

    Actually there is no need to link a spectre netlist to a layout. A spectre netlist is for simulation. : )  You can link a cdl netlist or a schematic to a layout. I don't quite understand your question so perhaps you might want to provide more info on the issue which you are facing.

    Best regards
    Quek

    • Post Points: 5
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Started by eactor at 12 May 2011 04:16 AM. Topic has 1 replies.