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 cross coverage between different bits in register and different bits in different register 

Last post Tue, May 17 2011 6:51 AM by StephenH. 1 replies.
Started by archvasu 11 May 2011 03:16 AM. Topic has 1 replies and 1390 views
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  • Wed, May 11 2011 3:16 AM

    • archvasu
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    • Joined on Fri, Dec 12 2008
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    cross coverage between different bits in register and different bits in different register Reply
    During every register access,  each of the fields of that register is covered. Say during a simulation every register is accessed within some stipulated time. At the end of that process I have an event, say – access_done.I want to have some cross cover checking  at this event. I want to cross reg1_field1, reg1_field2, reg2_field1, reg2_field3.How do I achieve it? In my env, registers and its field is declared as below   //                    NAME                   REGFILE              ADDR  reg_def INT_INDEX  REG_FILE         0x2200 {  //      name                                          : type          : mask        : reset value     : cov  reg_fld RPInterrupt                              : bit             : RW1C      : 0b0                  : cov ;  reg_fld LPInterrupt                                : bit            : RW1C      : 0b0                 : cov ;  reg_fld FSMErrInterrupt                       : bit            : RW1C      : 0b0                  : cov ;  reg_fld InterruptSignal                          : bit            : RW1C      : 0b0                   : cov ;  };    //                    NAME                           REGFILE              ADDR  reg_def INT_INDEX_MASK  REG_FILE         0x2204 {  //      name                                          : type         : mask         : reset value      : cov  reg_fld RPInterruptMask                      : bit            : RW           : 0b0                  : cov ;  reg_fld LPInterruptMask                       : bit            : RW           : 0b0                  : cov ;  reg_fld FSMErrInterruptMask               : bit            : RW           : 0b0                 : cov ;  reg_fld InterruptSignalMask                  : bit            : RW           : 0b0                 : cov ;  }; As per the packagestruct vr_ad_reg {   cover reg_access is {      item kind using per_instance,       ignore= kind == NONE;      item direction : vr_ad_rw_t =                        static_info.direction using when=static_info != NULL;      cross kind, direction;   }; The event I want to get cross done on isextend vr_ad_reg {   event access_done; };  Cross RPInterrupt, InterruptSignal, RPInterruptMask, InterruptSignalMask;This is the cross I want to check.Firstly how do I access the fields since these are items in a different cover group and next how to achieve cross at access_done event?  Thank you,Regards,

    Archana

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  • Tue, May 17 2011 6:51 AM

    • StephenH
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    Re: cross coverage between different bits in register and different bits in different register Reply

    You cannot perform a cross of items that are in different cover groups, because it's ambiguous about when the item samples are valid, if the groups have different sampling events.
    I would recommend that you simplify your plans to only use one sampling event, thus merging everything into one group. If you only want to define the items in order to cross them, them use the attribute "no_collect" to provent a hit counter being created for the raw item.

    To cross between registers, you have a couple of options:

    1. Put the coverage into the enclosing vr_ad_reg_file so it can make accesses into the int_index and int_index_mask register fields.
        You'd need to add a coverage event into the reg file and trigger it off the register's access event.

    2. Put the coverage into just one of the registers (e.e. int_index) , and also include a pointer to the other register (int_index_mask).
        This assumes that only one of the registers would besampling the coverag, so the reg_file approach is probably better.

     

    Steve Hobbs / Applications Engineer / Cadence Functional Verification
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Started by archvasu at 11 May 2011 03:16 AM. Topic has 1 replies.