Many questions. Is this a student project?
In answer to your question on connecting three devices to the SDRAM bus.
It is unlikely that there will be enough energy in the reflected waveforms to damage any of the components. However, this does not mean that your system will work. I suggest you use the SigXP tool to simulate your proposed layout and to constrain the design. Think carefully about termination resistors. With just three components on the bus, it will be difficult to wire anything other than a fly by topology.
You will need to look carefully at that level shifter. Does it act like a passive component in series with your transmission line, or does it act to break the transmission line in to two chunks. Either:
ADC - passive - SRAM - FPGA
ADC - levelshifter
Levelshifter - SRAM - FPGA
Tristating the level shifter or the FPGA, doesn't disconnect the copper traces, and therefore you should simulate to see what the reflection looks like.
Your second question. Yes, that is possible through timing constraints in the FPGA synthesis tool. It's not good practise to create an asynchronous delay though. Such delays vary with temperature, voltage, process etc. They also consume vast amounts of FPGA logic. Consider using the FPGA clock to generate a registered delay. You may be better served looking at a different solution, for example, how about clocking out the SRAM address on the other edge of the ADC clock? So if ADC presents data on the positive clock edge, then you change address on the negative.
I hope these pointers help.