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 Encounter Netlist files 

Last post Wed, Mar 30 2011 2:39 AM by Andrew Beckett. 1 replies.
Started by EveBell 29 Mar 2011 08:06 PM. Topic has 1 replies and 1327 views
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  • Tue, Mar 29 2011 8:06 PM

    • EveBell
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    • Joined on Tue, Mar 29 2011
    • Posts 8
    • Points 160
    Encounter Netlist files Reply


    If I have a  transistor level schematic and my simulations show that my circuit is working correctly in virtuoso, how can I generate the verilog netlist and source code to be imported/included for Encounter to design the layout?

    Thanks in advance! 

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    • Post Points: 20
  • Wed, Mar 30 2011 2:39 AM

    Re: Encounter Netlist files Reply

    You could use Tools->Simulation->NC Verilog (or Verilog XL) to invoke the Verilog netlister to produce a set of netlist files in the run directory. You'd probably need to concatenate them all together, or there's a solution on Cadence Online Support which explains how to set a variable which will produce a single netlist. I'm a bit busy, so I'll let you search for it yourself.

    Alternatively, contact Cadence Customer Support and go through this in more detail as a service request.



    • Post Points: 5
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Started by EveBell at 29 Mar 2011 08:06 PM. Topic has 1 replies.