I have a schematic in IC6.1.4 that uses two cds_thru instances. These two instances connect a single node to two output pins. When I neltist the schematic using CDL Out, the one cds_thru is replaced by a short circuit, and the other by a 100m resistor. Although this is not consistent, my design wiil still pass LVS. However, when I instance a symbol of that schematic onto a higher level, I find that the 100m resistor is now replaced by an open circuit. I've tested the same design in older versions of Virtuoso, and I did not see this problem. I've also made a small schematic in IC6.1.4, using only Cadence libraries and I see the exact same problem. Have you seen this before? Do you have any suggestions on a workaround?