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 Part-Select of an Array in SystemVerilog ... Not supported by Incisive ? 

Last post Thu, Dec 9 2010 1:24 AM by Almendrico. 3 replies.
Started by Almendrico 08 Dec 2010 10:17 AM. Topic has 3 replies and 3269 views
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  • Wed, Dec 8 2010 10:17 AM

    • Almendrico
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    • Limerick, Limerick
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    Part-Select of an Array in SystemVerilog ... Not supported by Incisive ? Reply

    Hi all,

    I am trying to do something very simple with SystemVerilog

    I have an 2-dimensional array defined as

    typedef logic [3:0] SR8x4 [0:7];

    and I just want to do a shift operation between the unpacked elements, i.e:

    SR8x4[1:7] <= SR8x4[0:6];

    However, I am getting the following errors:

               SR8x4[1:7] <= SR8x4[0:6];
                  |
    ncvlog: *E,NOPSOM (ShiftRegister.sv,27|14): Part-select or indexed part-select cannot be applied to memory [4.2.2(IEEE)].
              SR8x4[1:7] <= SR8x4[0:6];
                                |
    ncvlog: *E,NOPSOM (ShiftRegister.sv,27|28): Part-select or indexed part-select cannot be applied to memory [4.2.2(IEEE)].
            module worklib.ShiftRegister:sv
                    errors: 2, warnings: 0

    I believe the instruction is correct, so I think this SystemVerilog syntax is not supported by the tool ... I am using incisive 9.20

    Thanks

     

     

    • Post Points: 20
  • Wed, Dec 8 2010 10:28 AM

    • Shalom B
    • Top 200 Contributor
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    Re: Part-Select of an Array in SystemVerilog ... Not supported by Incisive ? Reply

    Correct, this is not yet implemented in Incisive 9.2.

    It is scheduled for sometime in 10.2

     Shalom

    Shalom.Bresticker@intel.com
    • Post Points: 20
  • Wed, Dec 8 2010 11:34 AM

    • tpylant
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    Re: Part-Select of an Array in SystemVerilog ... Not supported by Incisive ? Reply
    Here is a workaround until it is supported:
    module test;
      logic [3:0] arr [0:7] = '{0,1,2,3,4,5,6,7};

      initial begin
        $write("Pre");
        foreach (arr[i])
          $write(arr[i]);
        $write("\n");
        for (int l=1; <3; l++) begin
          foreach (arr[i])
            arr[i+1] <= arr[i];
          $write("%0d: ", l);
          foreach (arr[i])
            $write(arr[i]);
          $write("\n");
        end
      end
    endmodule

     

    Tim

    • Post Points: 20
  • Thu, Dec 9 2010 1:24 AM

    • Almendrico
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    Re: Part-Select of an Array in SystemVerilog ... Not supported by Incisive ? Reply

     Thank you guys for the answers

    • Post Points: 5
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Started by Almendrico at 08 Dec 2010 10:17 AM. Topic has 3 replies.