Thanks for the info. I tried doing what you've said i.e. executed the "cleanupSpecifyClockTree" command.
Following the cleanup of clock spec, I reported the latency to the same block clock pin and I see the same latency number.
I also did a report timing to the same block clock pin. I see the same latency number. So, it probably looks like the tool is not accounting for the macromodel definitions while building the clock tree to the block clock pins. Also, as I mentioned earlier, all the blocks are having the same latency values inspite of them having different macro model delay values.
This is something very important from a Top Level CTS perspective.
Any further suggestions please?