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 PSpice 

Last post Sat, Sep 25 2010 8:26 AM by tltoth. 6 replies.
Started by Tony Stark 24 Sep 2010 01:14 AM. Topic has 6 replies and 3133 views
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  • Fri, Sep 24 2010 1:14 AM

    • Tony Stark
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    • Gotham, Albania
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    PSpice Reply

    Good day!

    Please help me ("for dummies") with a problem!

    When I run PSpice, I see in *.out file(Allegro Design Entry 16.3):


    ERROR -- Node in is floating
    ERROR -- Node supply_0 is floating
    ERROR -- Node unnamed_1_bft92/plp_i1_e is floating
    ERROR -- Node diod is floating
    ERROR -- Node unnamed_1_bfr92a/plp_i2_b is floating
    ERROR -- Node unnamed_1_bfr92a/plp_i2_e is floating
    ERROR -- Node unnamed_1_r_i5_2 is floating
    ERROR -- Node X_X1.6 is floating
    ERROR -- Node X_X1.5 is floating
    ERROR -- Node X_X1.7 is floating
    ERROR -- Node X_X1.4 is floating
    ERROR -- Node X_X1.8 is floating
    ERROR -- Node X_X2.6 is floating
    ERROR -- Node X_X2.5 is floating
    ERROR -- Node X_X2.7 is floating
    ERROR -- Node X_X2.4 is floating
    ERROR -- Node X_X2.8 is floating  

    Why is that?

    • Post Points: 20
  • Fri, Sep 24 2010 4:50 AM

    • oldmouldy
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    Re: PSpice Reply

    You will also have a message in the session log that your design is missing a "0" node or symbol. PSpice requires that the design has a reference node called "0", you can call a net 0 or connect a 0 symbol from Place>Ground, pick the "0" symbol from the Capsym library, connect this to the reference net.

    • Post Points: 20
  • Fri, Sep 24 2010 7:50 AM

    • tltoth
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    Re: PSpice Reply

    if the error message still persist connect a high value (1 giga) grounded resistor to the node that the message indicates

    • Post Points: 20
  • Fri, Sep 24 2010 11:00 PM

    • Tony Stark
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    Re: PSpice Reply

     Thanks for the advices!

    I mixed up the "0" and "supply_0 "((((((

    What does the "supply_0"?

    • Post Points: 20
  • Sat, Sep 25 2010 1:15 AM

    • tltoth
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    Re: PSpice Reply

    It is a net name. Attach a picture of your schematic please. It will be easier to help you.

    • Post Points: 20
  • Sat, Sep 25 2010 5:46 AM

    • Tony Stark
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    Re: PSpice Reply

    See:

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  • Sat, Sep 25 2010 8:26 AM

    • tltoth
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    Re: PSpice Reply

    During DC Bias analysis each capacitor is assumed to be open circuit [xc=1/(wC), if w=0 xc->OO] and each inductor is short circuit.

    So there is no DC path between T2 emitter and R1 because of C2.

    Put an 1g resistor parallel to C1 and C2.

    • Post Points: 5
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Started by Tony Stark at 24 Sep 2010 01:14 AM. Topic has 6 replies.