Home > Community > Forums > Functional Verification > .vp file simulate

Email

* Required Fields

Recipients email * (separate multiple addresses with commas)

Your name *

Your email *

Message *

Contact Us

* Required Fields
First Name *

Last Name *

Email *

Company / Institution *

Comments: *

 .vp file simulate 

Last post Sat, Sep 11 2010 1:25 AM by digimind4ever. 0 replies.
Started by digimind4ever 11 Sep 2010 01:25 AM. Topic has 0 replies and 1451 views
Page 1 of 1 (1 items)
Sort Posts:
  • Sat, Sep 11 2010 1:25 AM

    .vp file simulate Reply

     Hello Friends,

    Can any one tell me how to simulate mixed signal .vp file in NC Sim?

    I have USB PHY Chip Model(analog + digital) in verilog. This model in .vp formet. Can any one tell me how can i simulate this model in NC Sim. Send me some useful link or steps.

     

    Best Regards:

    Digi0100ever

     

     

     

    Filed under:
    • Post Points: 5
Page 1 of 1 (1 items)
Sort Posts:
Started by digimind4ever at 11 Sep 2010 01:25 AM. Topic has 0 replies.