Thanks for your answare.
The problem is about the width of the void space between the spokes.
I have set all spacing constraint at 12.00mills for my test, shape to pin and shape to vias too. I have update the dynamic shape but the size is always 5 mills.
I have found these on my book "Complete PCB Design Using OrCAD® Capture and PCB Editor":
Thermal relief connections between plated through holes and copper areas on
positive planes are automatically generated by PCB Editor so flash symbols
need not be defined for positive layers. The inner diameter (ID) of the thermal
relief is defined by the pad diameter while the outer diameter (OD) is defined
by the diameter of the (thermal relief) circle in the padstack definition set in
the Padstack Designer.
If I set a clearance oversize in Shape->Global Dynamic shape Parameters->Clearances Tab, for thru pin at 7mills the width of void space become 12mills(5+7) but the oversize is applied to the other type of pin, without thermal relief.
What is the way to set the size of thermal relief void space between the spokes, without changing the clearence between dynamic shape (copper pour) and the pin connected to the signal nets?