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 MixedLanguage (Verilog+VHDL) Question 

Last post Thu, Aug 5 2010 1:31 PM by ashfaqh. 4 replies.
Started by ashfaqh 05 Aug 2010 01:14 AM. Topic has 4 replies and 3877 views
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  • Thu, Aug 5 2010 1:14 AM

    • ashfaqh
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    MixedLanguage (Verilog+VHDL) Question Reply

     Hello:

     I am using  ncsim   09.20-s016.

     I have a VHDL DUT.  The testbench top level is VHDL.  But, I have a few Verilog modules in the testbench.

    From one of the Verilog modules, I want to access (monitor) a signal inside the DUT (VHDL). 

    For example,

    if (top.level_1.level_2.sigout_1 == 1'b1) 
                $display("Posedge received at time: %d", $time) ;

     I get the following error:

     ncelab: *E,CUVHNF (...): Hierarchical name component lookup failed at 'top'.

     

    1.  Is it not possible to monitor a signal  inside a VHDL block from a Verilog module?

     

    Thanks.

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  • Thu, Aug 5 2010 7:47 AM

    • Mickey
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    Re: MixedLanguage (Verilog+VHDL) Question Reply

    • Post Points: 5
  • Thu, Aug 5 2010 8:03 AM

    • Mickey
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    Re: MixedLanguage (Verilog+VHDL) Question Reply
    Hello, If the top instance is vhdl the path should begin with a ":". With that in mind try (:top.level_1.level_2.sigout_1 == 1'b1). btw if you want to know the correct path to the object, you can comment out the problem code and go ahead and compile/elab/simulate in gui mode. when in the gui choose the sigout_1 signal from any of the simvision windows. then right mouse button and choose the describe option from the menu. The result will be the correct path to the object that should be used in the code. Hope that helps. Mickey
    • Post Points: 5
  • Thu, Aug 5 2010 10:38 AM

    • Mickey
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    Re: MixedLanguage (Verilog+VHDL) Question Reply

    I'm sorry, but I gave you incorrect information in the previous post.  From a verilog scope you can't directly reference an object that begins with a vhdl instance.  What you need to use is $nc_mirror to mirror that value of the object into a reg in a verilog scope.  You can then use the verilog object in the code.  for example:

    reg my_probe;

    initial

         $nc_mirror ("my_probe", ":top.level_1.level_2.sigout_1");

    always @(my_probe)

         if (my_probe == 1'b1);

              do_something;

    Feel free to email me at jrodrig@cadence.com if you have any questions.

    Sorry for the confusion.

    Mickey

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  • Thu, Aug 5 2010 1:31 PM

    • ashfaqh
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    Re: MixedLanguage (Verilog+VHDL) Question Reply

    Mickey:

    Your suggestion has worked very nicely!  Thank you very much for your help. 

    I wasn't aware of the $nc_mirror() task which allows VHDL signals to be probed from Verilog module.  

    I also successfully experimented by calling a user-defined Verilog task() from a verilog island module inside a VHDL top-level DUT -- that also works fine.

     For example, expanding on your example, the t_write() task call inside the island verilog module executes correctly in ncsim.

    Thanks again.

    -ashfaqh

     

    reg my_probe;

    initial

         $nc_mirror ("my_probe", ":top.level_1.level_2.sigout_1");    // sigout_1 is a VHDL signal

    always @(posedge my_probe)

       begin

            $display("my_probe asserted high at time: %d", $time) ;
            top_vhdl_level.vhdl_level_2.vhdl_level_3.verilog_module.t_write() ;    // t_write() is task inside verilog module

       end

     

    • Post Points: 5
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Started by ashfaqh at 05 Aug 2010 01:14 AM. Topic has 4 replies.