Your suggestion has worked very nicely! Thank you very much for your help.
I wasn't aware of the $nc_mirror() task which allows VHDL signals to be probed from Verilog module.
I also successfully experimented by calling a user-defined Verilog task() from a verilog island module inside a VHDL top-level DUT -- that also works fine.
For example, expanding on your example, the t_write() task call inside the island verilog module executes correctly in ncsim.
$nc_mirror ("my_probe", ":top.level_1.level_2.sigout_1"); // sigout_1 is a VHDL signal
always @(posedge my_probe) begin
$display("my_probe asserted high at time: %d", $time) ;
top_vhdl_level.vhdl_level_2.vhdl_level_3.verilog_module.t_write() ; // t_write() is task inside verilog module