I am facing a problem during the synthesis (RTL Compiler) which I cannot solve.
Here is the problem:
1) I have coded my digital design in VHDL.
2) The code has been simulated successfully.
3) In my digital design I also need SRAM and ROM macrocells.
a. So I used the ARTISAN memory generators for providing the memory macrocells.
4) I used Cadence RTL Compiler for the digital synthesis.
a. I initialized the libraries for the standard cells and the memory libraries in the .synth_init-File
b. I used a standard .tcl script for the synthesis with the Cadence RTL Compiler
1) The synthesis is successful, BUT I cannot connect the data and address buses to ROM and SRAM macrocells as you can see in the attached .bmp file.
2) Only WEN, CLK and CEN ports are mapped but not the DA,DB,QA,QB,AA,AB (Dual-Port SRAM and ROM) are connected…
1) At first I checked my VHDL code of the digital design.
a. Everything is OK. The problem cannot be the VHDL design.
2) In the following I tried to initialize the standard cell library excluding the memory libraries and to consider SRAM and ROM as empty modules.
a. The result was very interesting. Synthesis succeeded.
b. Now all the ports are mapped correctly, including the data and address buses to SRAM and ROM (empty) macrocells.
c. So I think it should be something wrong with the generated memory libraries.
3) I checked the generated ARTISAN memory lib files
a. In both lib files, SRAM and ROM, I found out that for the respective memory cells SRAM and ROM the parameters dont_use and dont_touch have been set to TRUE.
b. Because of that, after the synthesis, if I check the libraries with the command check_library I get the information that the SRAM and ROM macrocell are unusable.
c. For this problem I found something in the official Cadence documentation:
Forcing the Use of Specific Library Cells
You can instruct RTL Compiler to use a specific library cell even if the library’s vendor has
explicitly marked the cell as “don’t use” or “don’t touch”. The following sequential steps
illustrate how to force this behavior:
1. Set the preserve attribute to false on the particular library cell:
rc:/> set_attribute preserve false libcell_name
2. Next, set the avoid attribute to false on the same cell:
rc:/> set_attribute avoid false libcell_name
d. But even if I give these commands, it doesn’t work out yet. The data and address buses are not connected to the SRAM and ROM ports.
e. Somebody proposed me to use the following commands in my synthesis script:
set_attribute preserve true ROM
set_attribute preserve true RAM
It also didn’t work out!
1) I want to clarify that I checked all the possible dummy errors like:
a. Making sure that the function and grammar of my HDL code is correct before I run the synthesize.
b. Making sure that the port length of my data and address vectors is the same as the generated length of the SRAM and ROM data and address buses.
c. Making sure that the name of the components and of the libraries have been written correctly in the top design file.
d. And so on…
2) I think that something is not working out with the generated memory libraries, but I don't know what it could be...
Does anbody have any idea?
Thank you very much!