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 Name on .ENDS does not match .SUBCKT 

Last post Mon, Aug 5 2013 6:18 AM by alokt. 7 replies.
Started by 1PS1 23 Jun 2010 10:00 AM. Topic has 7 replies and 2693 views
Page 1 of 1 (8 items)
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  • Wed, Jun 23 2010 10:00 AM

    • 1PS1
    • Not Ranked
    • Joined on Wed, Jun 23 2010
    • Posts 1
    • Points 20
    Name on .ENDS does not match .SUBCKT Reply

    Why I am getting error message " Name on .ENDS does not match .SUBCKT" when I change parameters of an IC or transistor? Every subcircuitry has its ENDS.

    • Post Points: 20
  • Wed, Jun 30 2010 9:17 AM

    • oldmouldy
    • Top 10 Contributor
    • Joined on Tue, Jul 15 2008
    • Woking, Surrey
    • Posts 1,415
    • Points 24,170
    Re: Name on .ENDS does not match .SUBCKT Reply

    This might be because you have:

    .SUBCKT something <nodes>

    <netlist>

    .ENDS somethingelse

    in your sub-circuit definition. Otherwise, you may have exceeded the 80- character line length limit or you may have inappropriate white space in your model parameter text - this would usually yield more catastrophic results when the simulator runs though.

    • Post Points: 20
  • Thu, Aug 1 2013 2:55 PM

    • Murza
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    • Joined on Thu, Aug 1 2013
    • Posts 4
    • Points 50
    Re: Name on .ENDS does not match .SUBCKT Reply

    Hi Oldmouldy!

    I have the same troubles:  Name on .ENDS does not match .SUBCKT.

    I try to use your advise (to eliminate empty lines) but without positive result :o(

    Can you help me?

    Please see on part of log file from as follow and please tell me what is wrong?

    " *

    .SUBCKT INVERTER IIN IOUT IPS IGND

    $

    ERROR(ORPSIM-16363): Command invalid in subcircuit

    MI1 IOUT IIN IPS  IPS   PMOS W=15u L=3u

    MI2 IOUT IIN IGND IGND  NMOS W= 6u L=3u

    *

    .MODEL NMOS NMOS LEVEL=2 LD=0.15U TOX=2.0E-7

    + NSUB=5.36726E+15 VTO=0.743469 KP=8.00059E-05 GAMMA=0.543

    + PHI=0.6 U0=655.881 UEXP=0.157282 UCRIT=31443.8

    + DELTA=2.39824 VMAX=55260.9 XJ=0.25U LAMBDA=0.0367072

    + NFS=1E+12 NEFF=1.001 NSS=1E+11 TPG=1.0 RSH=70.00

    + CGDO=4.3E-10 CGSO=4.3E-10 CJ=0.0003 MJ=0.6585

    + CJSW=8.0E-10 MJSW=0.2402 PB=0.58

    *

    .MODEL PMOS PMOS LEVEL=2 LD=0.15U TOX=2.0E-7

    + NSUB=4.3318E+15 VTO=-0.738861 KP=2.70E-05 GAMMA=0.58

    + PHI=0.6 U0=261.977 UEXP=0.323932 UCRIT=65719.8

    + DELTA=1.79192 VMAX=25694 XJ=0.25U LAMBDA=0.0612279

    + NFS=1E+12 NEFF=1.001 NSS=1E+11 TPG=-1.0 RSH=120.6

    + CGDO=4.3E-10 CGSO=4.3E-10 CJ=0.0005 MJ=0.5052

    + CJSW=1.349E-10 MJSW=0.2417 PB=0.64

    *

    .ENDS INVERTER

    ------$

    ERROR(ORPSIM-16362): Name on .ENDS does not match .SUBCKT

    ERROR(ORPSIM-15108): Subcircuit INVERTER used by X_U1.XA0bar is undefined

    ERROR(ORPSIM-15108): Subcircuit INVERTER used by X_U1.XA1bar is undefined

    ERROR(ORPSIM-15108): Subcircuit INVERTER used by X_U1.XA0.XD1 is undefined

    ERROR(ORPSIM-15108): Subcircuit INVERTER used by X_U1.XA0.XD2 is undefined

    ERROR(ORPSIM-15108): Subcircuit INVERTER used by X_U1.XA1.XD1 is undefined

    ERROR(ORPSIM-15108): Subcircuit INVERTER used by X_U1.XA1.XD2 is undefined "

     

    What can I do? 

    • Post Points: 5
  • Thu, Aug 1 2013 3:23 PM

    • Murza
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    • Joined on Thu, Aug 1 2013
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    Re: Name on .ENDS does not match .SUBCKT Reply

    I delete INVERTER from line "ENDS INVERTER" and "Name on .ENDS does not match .SUBCKT" disappeared!

    But new problems on horizons...

    *

    DIGITAL CONTROLS

    *

    .SUBCKT INVERTER IIN IOUT IPS IGND

    $

    ERROR(ORPSIM-16363): Command invalid in subcircuit

    ERROR(ORPSIM-15108): Subcircuit INVERTER used by X_U1.XA0bar is undefined

    ERROR(ORPSIM-15108): Subcircuit INVERTER used by X_U1.XA1bar is undefined

    ERROR(ORPSIM-15108): Subcircuit INVERTER used by X_U1.XA0.XD1 is undefined

    ERROR(ORPSIM-15108): Subcircuit INVERTER used by X_U1.XA0.XD2 is undefined

    ERROR(ORPSIM-15108): Subcircuit INVERTER used by X_U1.XA1.XD1 is undefined

    ERROR(ORPSIM-15108): Subcircuit INVERTER used by X_U1.XA1.XD2 is undefined

    • Post Points: 20
  • Thu, Aug 1 2013 8:21 PM

    • alokt
    • Top 25 Contributor
    • Joined on Thu, Aug 21 2008
    • Noida, Uttar Pradesh
    • Posts 241
    • Points 3,470
    Re: Name on .ENDS does not match .SUBCKT Reply

    You may want to post complete .lib file. That would enable others to narrow down the exact issue. Based on details available this seems to be a case of nested subcircuit and that is not supported.

    Here is an example of nested subckt:

     .subckt AA 1 2
    R1 1 2 1
    X1 1 2 BB
    .subckt BB 1 2
    C1 1 2 1u
    .ends BB
    .ends

    PSpice would generate similar error when it encounter this. Definition of subckt "BB" should be moved out of "AA" in order to simulate a circuit with AA.

    Following would work

    .subckt AA 1 2
    R1 1 2 1
    X1 1 2 BB
    .ends
    .subckt BB 1 2
    C1 1 2 1u
    .ends BB

     Hope this helps.

    • Post Points: 35
  • Fri, Aug 2 2013 2:20 PM

    • Murza
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    • Joined on Thu, Aug 1 2013
    • Posts 4
    • Points 50
    Re: Name on .ENDS does not match .SUBCKT Reply

    Thank you Alokt for your answer! :o)

     Ab ovo...

    I want to simulate in Cadence Orcad 16.6 device with AD8253 IC from Analog Devices.

    I download Analog Devices model in form of AD8253.cir file which I try import. I modified this file because I found that pins numbers are completly mixed and not mached to real package ( I changed one line from ".SUBCKT AD8253       IN+ IN- A0 A1 WR* 99 50 OUT REF DGND" to ".SUBCKT AD8253       IN- DGND V- A0 A1 WR* OUT V+  REF IN+  ". I think that this change not flow on working of the model if I wrong please comment ). This way I have .lib file:

     

    * AD8253 SPICE Macromodel          Rev. D 5/2011

    * JCH / ADI

    * Temperature variations for the AD8253 are NOT included

    * in this model.

    *

    * Voltage Noise parameters for this model will closely model

    * typical AD8253 characteristics.  Current Noise parameters

    * will be slightly higher than typical AD8253 characteristics

    * due to modeling limitations.  

    * Noise is not modeled in Multisim.

    *                     inverting input

    *                     |   digital ground

    *                     |   |   negative supply

    *                     |   |   |  A0 (digital gain control)

    *                     |   |   |  |  A1 (digital gain control)

    *                     |   |   |  |  |   Digital Write

    *                     |   |   |  |  |   |  output

    *                     |   |   |  |  |   |  |   positive supply

    *                     |   |   |  |  |   |  |   |   reference

    *                     |   |   |  |  |   |  |   |   |   non-inverting input

    *                     |   |   |  |  |   |  |   |   |   |

    .SUBCKT AD8253       IN- DGND V- A0 A1 WR* OUT V+  REF IN+   

    .MODEL QPI PNP(VAF=100)

    .MODEL DOUT D(IS=5E-12)

    .MODEL DX D(IS=1E-16)

    .MODEL DNOI1 D(AF=1.5, KF=2E-10)

    .MODEL SWIA VSWITCH(VON=1.5,VOFF=1.2,ROFF=1E8)

    .MODEL SWBP VSWITCH(VON=3,VOFF=2.7)

    *

    * Resistor fb network, output amp

    *

    R3     104 202 10k

    R4     103 201 10k

    R5     201 OUT 10k

    R6     202 REF 10k

    *

    * DIGITAL CONTROL FOR GAIN SETTING

    * Settings are as given in AD8253 ds,

    * Table 5

    * A1 = A0 = 0,    G = 1

    * A1 = 0, A0 = 1, G = 10

    * A1 = 1, A0 = 0, G = 100

    * A1 = 1, A0 = 1, G = 1000

    *

    * DIGITAL CONTROLS ARE ASSUMED TO BE +5V

    * AND 0V. BEHAVIOR WITH OTHER DIGITAL INPUT

    * VOLTAGES IS NOT CHARACTERIZED.

    *

    * Digital power supply

    *

    VDD D99 0 5V

    *

    * Falling clock edge data latches with

    * switches. If WR* is higher than -1.5V,

    * switches pass latched data through, which

    * is latched on falling clock edge.

    *

    XA0 A0  WR*    A0LAT    A0bLAT D99 DGND DFF

    XA1 A1  WR*    A1LAT    A1bLAT D99 DGND DFF

    Vcntlin 0      cntlV    3V

    SLAT0   A0LAT  A0int    WR* cntlV SWIA

    SLAT1   A0bLAT A0barint WR* cntlV SWIA

    SLAT2   A1LAT  A1int    WR* cntlV SWIA

    SLAT3   A1bLAT A1barint WR* cntlV SWIA

    *

    * Switches for bypassing flipflops

    * If WR* is less than -3V, flipflops are

    * bypassed and A0 and A1 are passed

    * directly through.

    *

    SBP0   A0    A0int    0   WR* SWBP

    SBP1   A0bar A0barint 0   WR* SWBP

    XA0bar A0    A0bar    D99 DGND INVERTER

    SBP2   A1    A1int    0   WR* SWBP

    SBP3   A1bar A1barint 0   WR* SWBP

    XA1bar A1    A1bar    D99 DGND INVERTER

    *

    * GAIN CONTROL

    *

    * G = 1

    *

    SGC1  Rg- 105  A0barint 0 SWIA

    SGC2  105 103  A1barint 0 SWIA

    SGC3  106 Rg+  A0barint 0 SWIA

    SGC4  104 106  A1barint 0 SWIA

    *

    * G = 10

    *

    Rfb10a  103 107  6.75k

    Rfb10b  107 108  1.50k

    Rfb10c  108 104  6.75k

    SGC5    Rg- 109  A0int    0 SWIA

    SGC6    109 107  A1barint 0 SWIA

    SGC7    110 Rg+  A0int    0 SWIA

    SGC8    108 110  A1barint 0 SWIA

    *

    * G = 100

    *

    Rfb1e2a 103 111  19.8k

    Rfb1e2b 111 112  400

    Rfb1e2c 112 104  19.8k

    SGC9    Rg- 113  A0barint 0 SWIA

    SGC10   113 111  A1int    0 SWIA

    SGC11   114 Rg+  A0barint 0 SWIA

    SGC12   112 114  A1int    0 SWIA

    *

    * G = 1000

    *

    Rfb1e3a 103 115  49.95k

    Rfb1e3b 115 116  100

    Rfb1e3c 116 104  49.95k

    SGC13   Rg- 117  A0int 0 SWIA

    SGC14   117 115  A1int 0 SWIA

    SGC15   118 Rg+  A0int 0 SWIA

    SGC16   116 118  A1int 0 SWIA

    *

    * INTERNAL VOLTAGE REFERENCE

    *

    RREF1 99 90  500k

    RREF2 90 50  500k

    CREF1 90  0  5uF

    EREF1 98  0  90 0 1

    *

    * CURRENT CONSUMPTION CORRECTION

    *

    ICORR+ 99  0 1.6m

    ICORR-  0 50 1.5m

    *

    * INPUT STAGE COMPARE AMPLIFIER #1

    *

    Q1A        A4   A3  A01  QPI

    Q2A        A6   A9  A2   QPI

    RE1A       A01  A8  415

    RE2A       A2   A8  415

    RC1A       A5   A4  5k

    RC2A       A5   A6  5k

    VADJA      50   A5  1.5V

    IBIASA     99   A8  1m

    * Bias current compensation

    VBIASMONA A10   A3   0V

    FBIASCMPA   0   IN- VBIASMONA 0.9988

    * noise, -PS, offset V introduction

    ENOISA     IN-  A11  A53 98 1

    VOSA       A11  A10  158uV

    EPSRA-     Rg-  A7   98 A62 1

    VPSRA-     A7   A9  140.8uV

    D1A        IN-  99   DX

    D2A        50   IN-   DX

    *

    * VOLTAGE NOISE STAGE COMP AMP #1

    *

    DN1A    A51 A52 DNOI1

    VN1A    A51  98 0.615

    VMEASA  A52  98 0

    RNOI1A  A52  98 3e-4

    *

    F1A     A53 98 VMEASA 1

    RNOI2A  A53 98 1

    *

    * -PS PERTURBATION STAGE COMP AMP #1

    *

    EPSA1   A61  98 50 0 1

    RPSA1   A61 A62 100K

    RPSA2   A62  98 0.15

    CPSA1   A61 A62 450p

    *

    * GAIN STAGE WITH DOMINANT POLE = 0.8Hz COMP AMP #1

    *

    GP2A   A21  98 A6 A4 1

    RP2A   A21  98 1E7

    CP2A   A21  98 2e-8

    *

    * VOLTAGE LIMITING CIRCUITRY COMP AMP #1

    *

    VLIM1A    99 A23 1.5

    DOUT1A   A21 A23 DOUT

    VLIM2A   A24  50 1.75

    DOUT2A   A24 A21 DOUT

    *

    * SUPPLY CURRENT ADJUSTMENT COMP AMP #1

    *

    FADJ1A  0 99 VLIM1A 1

    FADJ2A 50  0 VLIM2A 1

    *

    * INTERMEDIATE GAIN STAGE COMP AMP #1

    *

    GP3A   A22  98 A21 98 1E-3

    RP3A   A22  98 1k

    *

    * CURRENT LIMITING COMP AMP #1

    *

    DILIM1A A22 A25 DOUT

    VILIM1A A31 A25 0.415

    DILIM2A A26 A22 DOUT

    VILIM2A A26 A31 0.415

    *

    * OUTPUT STAGE COMP AMP #1

    * Node 103 = CA #1 output node

    *

    VMO1A     99 A40   0

    VMO2A    A42  50   0

    VMO3A    A31 103   0

    ROUT1A   A40 A31  10

    ROUT2A   A42 A31  10

    GOUT1A   A31 A40  99 A22 0.1

    GOUT2A   A42 A31 A22  50 0.1

    *

    * INPUT STAGE COMPARE AMPLIFIER #2

    *

    Q1B     B4  B3  B1   QPI

    Q2B     B6  Rg+ B2   QPI

    RE1B    B1  B8  415

    RE2B    B2  B8  415

    RC1B    B5  B4  5k

    RC2B    B5  B6  5k

    VADJB   50  B5  1.5V

    IBIASB  99  B8  1m

    * Bias current compensation

    VBIASMONB B10 B3 0V

    FBIASCMPB 0 IN+ VBIASMONB 0.9988

    * CM, +PS, noise introduction

    ECMB3  IN+  B7   B62 98 1

    ENOISB  B7  B9   B53 98 1

    EPSRB+  B9  B10  B64 98 1

    D1B     IN+ 99  DX

    D2B     50  IN+  DX

    *

    * VOLTAGE NOISE STAGE COMP AMP #2

    *

    DN1B    B51 B52 DNOI1

    VN1B    B51 98  0.615

    VMEASB  B52 98  0

    RNOI1B  B52 98  3e-4

    *

    F1B     B53 98 VMEASB 1

    RNOI2B  B53 98 1

    *

    * CM VOLTAGE STAGE COMP AMP #2

    * zero at 31kHz

    *

    ECMB1   B60  98 IN+ 98 1

    ECMB2   B61 B60 IN- 98 1

    RCMB1   B61 B62 100K

    CCMB1   B61 B62 50p

    RCMB2   B62  98 0.19

    *

    * +PS PERTURBATION STAGE COMP AMP #2

    *

    EPSB1   B63  98 99 0 1

    RPSB1   B63 B64 100K

    RPSB2   B64  98 0.1

    CPSB1   B63 B64 100p

    *

    * GAIN STAGE WITH DOMINANT POLE COMP AMP #2

    *

    GP2B   B21  98 B6 B4 1

    RP2B   B21  98 1E7

    CP2B   B21  98 2e-8

    *

    * VOLTAGE LIMITING CIRCUITRY COMP AMP #2

    *

    VLIM1B    99 B23 1.5

    DOUT1B   B21 B23 DOUT

    VLIM2B   B24  50 1.75

    DOUT2B   B24 B21 DOUT

    *

    * SUPPLY CURRENT ADJUSTMENT COMP AMP #2

    *

    FADJ1B  0 99 VLIM1B 1

    FADJ2B 50  0 VLIM2B 1

    *

    * INTERMEDIATE GAIN STAGE COMP AMP #2

    *

    GP3B   B22  98 B21 98 1E-3

    RP3B   B22  98 1k

    *

    * CURRENT LIMITING COMP AMP #2

    *

    DILIM1B B22 B25 DOUT

    VILIM1B B31 B25 0.415

    DILIM2B B26 B22 DOUT

    VILIM2B B26 B31 0.415

    *

    * OUTPUT STAGE COMP AMP #2

    * Node 104 = CA #2 output node

    *

    VMO1B     99 B40   0

    VMO2B    B42  50   0

    VMO3B    B31 104   0

    ROUT1B   B40 B31  10

    ROUT2B   B42 B31  10

    GOUT1B   B31 B40  99 B22 0.1

    GOUT2B   B42 B31 B22  50 0.1

    *

    * INPUT STAGE OUTPUT AMPLIFIER

    *

    Q1C    C4   C3   C1  QPI

    Q2C    C6  C11   C2  QPI

    RE1C   C1   C8  175

    RE2C   C2   C8  175

    RC1C   50   C4  5.75k

    RC2C   50   C6  5.75k

    CC1C   C4   C6  0.7p

    *

    * Introduces second pole

    * P2 = 1/(2*PI*2Rc*Cc1)

    *

    * Offset V, CM, PS, voltage noise introduction

    *

    EPSRC+ 202   C9  C64 98 1

    ECMC3   C9   C7  C62 98 1

    ENOISC  C7   C5  C53 98 1

    VOSC    C5   C3  642.5uV

    EPSRC- 201  C12  C66 98 1

    VPSRC- C12  C11  58.5uV

    D1C     C3   99  DX

    D2C     50   C3  DX

    IBIASC  99   C8  1m

    *

    * VOLTAGE NOISE STAGE OUTPUT AMP

    *

    DN1C   C51 C52 DNOI1

    VN1C   C51  98 0.648

    VMEASC C52  98 0

    RNOI1C C52  98 1.1e-4

     

    F1C    C53  98 VMEASC 1

    RNOI2C C53  98 1

    *

    * CM VOLTAGE STAGE OUTPUT AMP

    * zero at 3kHz

    *

    ECMC1   C60  98 IN+ 98 1

    ECMC2   C61 C60 IN- 98 1

    RCMC1   C61 C62 100K

    CCMC1   C61 C62 520p

    RCMC2   C62  98 0.29

    *

    * +PS PERTURBATION STAGE OUTPUT AMP

    *

    EPSC1   C63  98 99 0 1

    RPSC1   C63 C64 100K

    RPSC2   C64  98 0.39

    CPSC1   C63 C64 380p

    *

    * -PS PERTURBATION STAGE OUTPUT AMP

    *

    EPSC2   C65  98 50 0 1

    RPSC3   C65 C66 100K

    RPSC4   C66  98 0.39

    CPSC2   C65 C66 20n

    *

    * GAIN STAGE WITH DOMINANT POLE = 65mHz OUTPUT AMP

    *

    GP2C   C21 98 C6 C4 1

    RP2C   C21 98 1E7

    CP2C   C21 98 2.8E-7

    *

    * VOLTAGE LIMITING CIRCUITRY OUTPUT AMP

    *

    VLIM1C    99 C23 1.96

    DOUT1C   C21 C23 DOUT

    VLIM2C   C24  50 2.1

    DOUT2C   C24 C21 DOUT

    *

    * SUPPLY CURRENT ADJUSTMENT OUTPUT AMP

    *

    FADJ1C  0 99 VLIM1C 1

    FADJ2C 50  0 VLIM2C 1

    *

    * INTERMEDIATE GAIN STAGE OUTPUT AMP

    *

    GP3C   C22  98 C21 98 1E-3

    RP3C   C22  98 1k

    CP3C   C22  98 4pF

    *

    * CURRENT LIMITING OUTPUT AMP

    *

    DILIM1C C22 C25 DOUT

    VILIM1C C31 C25 0.415

    DILIM2C C26 C22 DOUT

    VILIM2C C26 C31 0.415

    *

    * OUTPUT STAGE OUTPUT AMP

    *

    VMO1C     99 C40   0

    VMO2C    C42  50   0

    VMO3C    C31 OUT   0

    ROUT1C   C40 C31  10

    ROUT2C   C42 C31  10

    GOUT1C   C31 C40  99 C22 0.1

    GOUT2C   C42 C31 C22  50 0.1

    *

    * DIGITAL CONTROLS

    *

    .SUBCKT INVERTER IIN IOUT IPS IGND

    MI1 IOUT IIN IPS  IPS   PMOS W=15u L=3u

    MI2 IOUT IIN IGND IGND  NMOS W= 6u L=3u

    *

    .MODEL NMOS NMOS LEVEL=2 LD=0.15U TOX=2.0E-7

    + NSUB=5.36726E+15 VTO=0.743469 KP=8.00059E-05 GAMMA=0.543

    + PHI=0.6 U0=655.881 UEXP=0.157282 UCRIT=31443.8

    + DELTA=2.39824 VMAX=55260.9 XJ=0.25U LAMBDA=0.0367072

    + NFS=1E+12 NEFF=1.001 NSS=1E+11 TPG=1.0 RSH=70.00

    + CGDO=4.3E-10 CGSO=4.3E-10 CJ=0.0003 MJ=0.6585

    + CJSW=8.0E-10 MJSW=0.2402 PB=0.58

    *

    .MODEL PMOS PMOS LEVEL=2 LD=0.15U TOX=2.0E-7

    + NSUB=4.3318E+15 VTO=-0.738861 KP=2.70E-05 GAMMA=0.58

    + PHI=0.6 U0=261.977 UEXP=0.323932 UCRIT=65719.8

    + DELTA=1.79192 VMAX=25694 XJ=0.25U LAMBDA=0.0612279

    + NFS=1E+12 NEFF=1.001 NSS=1E+11 TPG=-1.0 RSH=120.6

    + CGDO=4.3E-10 CGSO=4.3E-10 CJ=0.0005 MJ=0.5052

    + CJSW=1.349E-10 MJSW=0.2417 PB=0.64

    *

    .ENDS 

    *

    .SUBCKT NAND NDNIN1 NDNIN2 NDNOUT NDNPS NDNGND

    MN1 NDNOUT NDNIN1 NDNPS  NDNPS  PMOS W=15u L=3u

    MN2 NDNOUT NDNIN2 NDNPS  NDNPS  PMOS W=15u L=3u

    MN3 NDNOUT NDNIN2 10     NDNGND NMOS W= 6u L=3u

    MN4 10     NDNIN1 NDNGND NDNGND NMOS W= 6u L=3u

    *

    * SPICE LEVEL 2 Model for 1.2 mu Process

    *

    .MODEL NMOS NMOS LEVEL=2 LD=0.15U TOX=2.0E-7

    + NSUB=5.36726E+15 VTO=0.743469 KP=8.00059E-05 GAMMA=0.543

    + PHI=0.6 U0=655.881 UEXP=0.157282 UCRIT=31443.8

    + DELTA=2.39824 VMAX=55260.9 XJ=0.25U LAMBDA=0.0367072

    + NFS=1E+12 NEFF=1.001 NSS=1E+11 TPG=1.0 RSH=70.00

    + CGDO=4.3E-10 CGSO=4.3E-10 CJ=0.0003 MJ=0.6585

    + CJSW=8.0E-10 MJSW=0.2402 PB=0.58

    *

    .MODEL PMOS PMOS LEVEL=2 LD=0.15U TOX=2.0E-7

    + NSUB=4.3318E+15 VTO=-0.738861 KP=2.70E-05 GAMMA=0.58

    + PHI=0.6 U0=261.977 UEXP=0.323932 UCRIT=65719.8

    + DELTA=1.79192 VMAX=25694 XJ=0.25U LAMBDA=0.0612279

    + NFS=1E+12 NEFF=1.001 NSS=1E+11 TPG=-1.0 RSH=120.6

    + CGDO=4.3E-10 CGSO=4.3E-10 CJ=0.0005 MJ=0.5052

    + CJSW=1.349E-10 MJSW=0.2417 PB=0.64

    *

    .ENDS

    *

    .SUBCKT JKFF FFJ FFK FFEN FFQ FFQb FFPS FFGND

    * Qb = Qbar

    XJK1 FFJ  FFEN    3  FFPS FFGND NAND

    XJK2 FFK  FFEN    4  FFPS FFGND NAND

    XJK3   3  FFQb  FFQ  FFPS FFGND NAND

    XJK4   4  FFQ   FFQb FFPS FFGND NAND

    *

    .ENDS

    *

    .SUBCKT DFF FFD FFWR FFQ FFQb FFPS FFGND

    * D flipflop with data lock on falling clock edge

    XD1 FFD   FFDb   FFPS  FFGND INVERTER

    XD2 FFWR  FFWRb  FFPS  FFGND INVERTER

    XD3 FFD   FFDb   FFWR   11   12 FFPS FFGND JKFF

    XD4  11     12   FFWRb FFQ FFQb FFPS FFGND JKFF

    *

    .ENDS

    .ENDS AD8253

     

    What do you think about this problem?

    There are the form with last changes which are descripd in my previous post (deleting of "INVERTER" word).

    • Post Points: 20
  • Fri, Aug 2 2013 2:53 PM

    • Murza
    • Not Ranked
    • Joined on Thu, Aug 1 2013
    • Posts 4
    • Points 50
    Re: Name on .ENDS does not match .SUBCKT Reply

    Hello It's me again!

    Because in file placed higher was more than two changes I send you first version (only the line with pins are changed):

     

    * AD8253 SPICE Macromodel          Rev. D 5/2011

    * JCH / ADI

    * Temperature variations for the AD8253 are NOT included

    * in this model.

    *

    * Voltage Noise parameters for this model will closely model

    * typical AD8253 characteristics.  Current Noise parameters

    * will be slightly higher than typical AD8253 characteristics

    * due to modeling limitations.  

    * Noise is not modeled in Multisim.

    *                     inverting input

    *                     |   digital ground

    *                     |   |   negative supply

    *                     |   |   |  A0 (digital gain control)

    *                     |   |   |  |  A1 (digital gain control)

    *                     |   |   |  |  |   Digital Write

    *                     |   |   |  |  |   |  output

    *                     |   |   |  |  |   |  |   positive supply

    *                     |   |   |  |  |   |  |   |   reference

    *                     |   |   |  |  |   |  |   |   |   non-inverting input

    *                     |   |   |  |  |   |  |   |   |   |

    .SUBCKT AD8253       IN- DGND V- A0 A1 WR* OUT V+  REF IN+   

    .MODEL QPI PNP(VAF=100)

    .MODEL DOUT D(IS=5E-12)

    .MODEL DX D(IS=1E-16)

    .MODEL DNOI1 D(AF=1.5, KF=2E-10)

    .MODEL SWIA VSWITCH(VON=1.5,VOFF=1.2,ROFF=1E8)

    .MODEL SWBP VSWITCH(VON=3,VOFF=2.7)

    *

    * Resistor fb network, output amp

    *

    R3     104 202 10k

    R4     103 201 10k

    R5     201 OUT 10k

    R6     202 REF 10k

    *

    * DIGITAL CONTROL FOR GAIN SETTING

    * Settings are as given in AD8253 ds,

    * Table 5

    * A1 = A0 = 0,    G = 1

    * A1 = 0, A0 = 1, G = 10

    * A1 = 1, A0 = 0, G = 100

    * A1 = 1, A0 = 1, G = 1000

    *

    * DIGITAL CONTROLS ARE ASSUMED TO BE +5V

    * AND 0V. BEHAVIOR WITH OTHER DIGITAL INPUT

    * VOLTAGES IS NOT CHARACTERIZED.

    *

    * Digital power supply

    *

    VDD D99 0 5V

    *

    * Falling clock edge data latches with

    * switches. If WR* is higher than -1.5V,

    * switches pass latched data through, which

    * is latched on falling clock edge.

    *

    XA0 A0  WR*    A0LAT    A0bLAT D99 DGND DFF

    XA1 A1  WR*    A1LAT    A1bLAT D99 DGND DFF

    Vcntlin 0      cntlV    3V

    SLAT0   A0LAT  A0int    WR* cntlV SWIA

    SLAT1   A0bLAT A0barint WR* cntlV SWIA

    SLAT2   A1LAT  A1int    WR* cntlV SWIA

    SLAT3   A1bLAT A1barint WR* cntlV SWIA

    *

    * Switches for bypassing flipflops

    * If WR* is less than -3V, flipflops are

    * bypassed and A0 and A1 are passed

    * directly through.

    *

    SBP0   A0    A0int    0   WR* SWBP

    SBP1   A0bar A0barint 0   WR* SWBP

    XA0bar A0    A0bar    D99 DGND INVERTER

    SBP2   A1    A1int    0   WR* SWBP

    SBP3   A1bar A1barint 0   WR* SWBP

    XA1bar A1    A1bar    D99 DGND INVERTER

    *

    * GAIN CONTROL

    *

    * G = 1

    *

    SGC1  Rg- 105  A0barint 0 SWIA

    SGC2  105 103  A1barint 0 SWIA

    SGC3  106 Rg+  A0barint 0 SWIA

    SGC4  104 106  A1barint 0 SWIA

    *

    * G = 10

    *

    Rfb10a  103 107  6.75k

    Rfb10b  107 108  1.50k

    Rfb10c  108 104  6.75k

    SGC5    Rg- 109  A0int    0 SWIA

    SGC6    109 107  A1barint 0 SWIA

    SGC7    110 Rg+  A0int    0 SWIA

    SGC8    108 110  A1barint 0 SWIA

    *

    * G = 100

    *

    Rfb1e2a 103 111  19.8k

    Rfb1e2b 111 112  400

    Rfb1e2c 112 104  19.8k

    SGC9    Rg- 113  A0barint 0 SWIA

    SGC10   113 111  A1int    0 SWIA

    SGC11   114 Rg+  A0barint 0 SWIA

    SGC12   112 114  A1int    0 SWIA

    *

    * G = 1000

    *

    Rfb1e3a 103 115  49.95k

    Rfb1e3b 115 116  100

    Rfb1e3c 116 104  49.95k

    SGC13   Rg- 117  A0int 0 SWIA

    SGC14   117 115  A1int 0 SWIA

    SGC15   118 Rg+  A0int 0 SWIA

    SGC16   116 118  A1int 0 SWIA

    *

    * INTERNAL VOLTAGE REFERENCE

    *

    RREF1 99 90  500k

    RREF2 90 50  500k

    CREF1 90  0  5uF

    EREF1 98  0  90 0 1

    *

    * CURRENT CONSUMPTION CORRECTION

    *

    ICORR+ 99  0 1.6m

    ICORR-  0 50 1.5m

    *

    * INPUT STAGE COMPARE AMPLIFIER #1

    *

    Q1A        A4   A3  A01  QPI

    Q2A        A6   A9  A2   QPI

    RE1A       A01  A8  415

    RE2A       A2   A8  415

    RC1A       A5   A4  5k

    RC2A       A5   A6  5k

    VADJA      50   A5  1.5V

    IBIASA     99   A8  1m

    * Bias current compensation

    VBIASMONA A10   A3   0V

    FBIASCMPA   0   IN- VBIASMONA 0.9988

    * noise, -PS, offset V introduction

    ENOISA     IN-  A11  A53 98 1

    VOSA       A11  A10  158uV

    EPSRA-     Rg-  A7   98 A62 1

    VPSRA-     A7   A9  140.8uV

    D1A        IN-  99   DX

    D2A        50   IN-   DX

    *

    * VOLTAGE NOISE STAGE COMP AMP #1

    *

    DN1A    A51 A52 DNOI1

    VN1A    A51  98 0.615

    VMEASA  A52  98 0

    RNOI1A  A52  98 3e-4

    *

    F1A     A53 98 VMEASA 1

    RNOI2A  A53 98 1

    *

    * -PS PERTURBATION STAGE COMP AMP #1

    *

    EPSA1   A61  98 50 0 1

    RPSA1   A61 A62 100K

    RPSA2   A62  98 0.15

    CPSA1   A61 A62 450p

    *

    * GAIN STAGE WITH DOMINANT POLE = 0.8Hz COMP AMP #1

    *

    GP2A   A21  98 A6 A4 1

    RP2A   A21  98 1E7

    CP2A   A21  98 2e-8

    *

    * VOLTAGE LIMITING CIRCUITRY COMP AMP #1

    *

    VLIM1A    99 A23 1.5

    DOUT1A   A21 A23 DOUT

    VLIM2A   A24  50 1.75

    DOUT2A   A24 A21 DOUT

    *

    * SUPPLY CURRENT ADJUSTMENT COMP AMP #1

    *

    FADJ1A  0 99 VLIM1A 1

    FADJ2A 50  0 VLIM2A 1

    *

    * INTERMEDIATE GAIN STAGE COMP AMP #1

    *

    GP3A   A22  98 A21 98 1E-3

    RP3A   A22  98 1k

    *

    * CURRENT LIMITING COMP AMP #1

    *

    DILIM1A A22 A25 DOUT

    VILIM1A A31 A25 0.415

    DILIM2A A26 A22 DOUT

    VILIM2A A26 A31 0.415

    *

    * OUTPUT STAGE COMP AMP #1

    * Node 103 = CA #1 output node

    *

    VMO1A     99 A40   0

    VMO2A    A42  50   0

    VMO3A    A31 103   0

    ROUT1A   A40 A31  10

    ROUT2A   A42 A31  10

    GOUT1A   A31 A40  99 A22 0.1

    GOUT2A   A42 A31 A22  50 0.1

    *

    * INPUT STAGE COMPARE AMPLIFIER #2

    *

    Q1B     B4  B3  B1   QPI

    Q2B     B6  Rg+ B2   QPI

    RE1B    B1  B8  415

    RE2B    B2  B8  415

    RC1B    B5  B4  5k

    RC2B    B5  B6  5k

    VADJB   50  B5  1.5V

    IBIASB  99  B8  1m

    * Bias current compensation

    VBIASMONB B10 B3 0V

    FBIASCMPB 0 IN+ VBIASMONB 0.9988

    * CM, +PS, noise introduction

    ECMB3  IN+  B7   B62 98 1

    ENOISB  B7  B9   B53 98 1

    EPSRB+  B9  B10  B64 98 1

    D1B     IN+ 99  DX

    D2B     50  IN+  DX

    *

    * VOLTAGE NOISE STAGE COMP AMP #2

    *

    DN1B    B51 B52 DNOI1

    VN1B    B51 98  0.615

    VMEASB  B52 98  0

    RNOI1B  B52 98  3e-4

    *

    F1B     B53 98 VMEASB 1

    RNOI2B  B53 98 1

    *

    * CM VOLTAGE STAGE COMP AMP #2

    * zero at 31kHz

    *

    ECMB1   B60  98 IN+ 98 1

    ECMB2   B61 B60 IN- 98 1

    RCMB1   B61 B62 100K

    CCMB1   B61 B62 50p

    RCMB2   B62  98 0.19

    *

    * +PS PERTURBATION STAGE COMP AMP #2

    *

    EPSB1   B63  98 99 0 1

    RPSB1   B63 B64 100K

    RPSB2   B64  98 0.1

    CPSB1   B63 B64 100p

    *

    * GAIN STAGE WITH DOMINANT POLE COMP AMP #2

    *

    GP2B   B21  98 B6 B4 1

    RP2B   B21  98 1E7

    CP2B   B21  98 2e-8

    *

    * VOLTAGE LIMITING CIRCUITRY COMP AMP #2

    *

    VLIM1B    99 B23 1.5

    DOUT1B   B21 B23 DOUT

    VLIM2B   B24  50 1.75

    DOUT2B   B24 B21 DOUT

    *

    * SUPPLY CURRENT ADJUSTMENT COMP AMP #2

    *

    FADJ1B  0 99 VLIM1B 1

    FADJ2B 50  0 VLIM2B 1

    *

    * INTERMEDIATE GAIN STAGE COMP AMP #2

    *

    GP3B   B22  98 B21 98 1E-3

    RP3B   B22  98 1k

    *

    * CURRENT LIMITING COMP AMP #2

    *

    DILIM1B B22 B25 DOUT

    VILIM1B B31 B25 0.415

    DILIM2B B26 B22 DOUT

    VILIM2B B26 B31 0.415

    *

    * OUTPUT STAGE COMP AMP #2

    * Node 104 = CA #2 output node

    *

    VMO1B     99 B40   0

    VMO2B    B42  50   0

    VMO3B    B31 104   0

    ROUT1B   B40 B31  10

    ROUT2B   B42 B31  10

    GOUT1B   B31 B40  99 B22 0.1

    GOUT2B   B42 B31 B22  50 0.1

    *

    * INPUT STAGE OUTPUT AMPLIFIER

    *

    Q1C    C4   C3   C1  QPI

    Q2C    C6  C11   C2  QPI

    RE1C   C1   C8  175

    RE2C   C2   C8  175

    RC1C   50   C4  5.75k

    RC2C   50   C6  5.75k

    CC1C   C4   C6  0.7p

    *

    * Introduces second pole

    * P2 = 1/(2*PI*2Rc*Cc1)

    *

    * Offset V, CM, PS, voltage noise introduction

    *

    EPSRC+ 202   C9  C64 98 1

    ECMC3   C9   C7  C62 98 1

    ENOISC  C7   C5  C53 98 1

    VOSC    C5   C3  642.5uV

    EPSRC- 201  C12  C66 98 1

    VPSRC- C12  C11  58.5uV

    D1C     C3   99  DX

    D2C     50   C3  DX

    IBIASC  99   C8  1m

    *

    * VOLTAGE NOISE STAGE OUTPUT AMP

    *

    DN1C   C51 C52 DNOI1

    VN1C   C51  98 0.648

    VMEASC C52  98 0

    RNOI1C C52  98 1.1e-4

     

    F1C    C53  98 VMEASC 1

    RNOI2C C53  98 1

    *

    * CM VOLTAGE STAGE OUTPUT AMP

    * zero at 3kHz

    *

    ECMC1   C60  98 IN+ 98 1

    ECMC2   C61 C60 IN- 98 1

    RCMC1   C61 C62 100K

    CCMC1   C61 C62 520p

    RCMC2   C62  98 0.29

    *

    * +PS PERTURBATION STAGE OUTPUT AMP

    *

    EPSC1   C63  98 99 0 1

    RPSC1   C63 C64 100K

    RPSC2   C64  98 0.39

    CPSC1   C63 C64 380p

    *

    * -PS PERTURBATION STAGE OUTPUT AMP

    *

    EPSC2   C65  98 50 0 1

    RPSC3   C65 C66 100K

    RPSC4   C66  98 0.39

    CPSC2   C65 C66 20n

    *

    * GAIN STAGE WITH DOMINANT POLE = 65mHz OUTPUT AMP

    *

    GP2C   C21 98 C6 C4 1

    RP2C   C21 98 1E7

    CP2C   C21 98 2.8E-7

    *

    * VOLTAGE LIMITING CIRCUITRY OUTPUT AMP

    *

    VLIM1C    99 C23 1.96

    DOUT1C   C21 C23 DOUT

    VLIM2C   C24  50 2.1

    DOUT2C   C24 C21 DOUT

    *

    * SUPPLY CURRENT ADJUSTMENT OUTPUT AMP

    *

    FADJ1C  0 99 VLIM1C 1

    FADJ2C 50  0 VLIM2C 1

    *

    * INTERMEDIATE GAIN STAGE OUTPUT AMP

    *

    GP3C   C22  98 C21 98 1E-3

    RP3C   C22  98 1k

    CP3C   C22  98 4pF

    *

    * CURRENT LIMITING OUTPUT AMP

    *

    DILIM1C C22 C25 DOUT

    VILIM1C C31 C25 0.415

    DILIM2C C26 C22 DOUT

    VILIM2C C26 C31 0.415

    *

    * OUTPUT STAGE OUTPUT AMP

    *

    VMO1C     99 C40   0

    VMO2C    C42  50   0

    VMO3C    C31 OUT   0

    ROUT1C   C40 C31  10

    ROUT2C   C42 C31  10

    GOUT1C   C31 C40  99 C22 0.1

    GOUT2C   C42 C31 C22  50 0.1

    *

    * DIGITAL CONTROLS

    *

    .SUBCKT INVERTER IIN IOUT IPS IGND

    MI1 IOUT IIN IPS  IPS   PMOS W=15u L=3u

    MI2 IOUT IIN IGND IGND  NMOS W= 6u L=3u

     

    .MODEL NMOS NMOS LEVEL=2 LD=0.15U TOX=2.0E-7

    + NSUB=5.36726E+15 VTO=0.743469 KP=8.00059E-05 GAMMA=0.543

    + PHI=0.6 U0=655.881 UEXP=0.157282 UCRIT=31443.8

    + DELTA=2.39824 VMAX=55260.9 XJ=0.25U LAMBDA=0.0367072

    + NFS=1E+12 NEFF=1.001 NSS=1E+11 TPG=1.0 RSH=70.00

    + CGDO=4.3E-10 CGSO=4.3E-10 CJ=0.0003 MJ=0.6585

    + CJSW=8.0E-10 MJSW=0.2402 PB=0.58

     

    .MODEL PMOS PMOS LEVEL=2 LD=0.15U TOX=2.0E-7

    + NSUB=4.3318E+15 VTO=-0.738861 KP=2.70E-05 GAMMA=0.58

    + PHI=0.6 U0=261.977 UEXP=0.323932 UCRIT=65719.8

    + DELTA=1.79192 VMAX=25694 XJ=0.25U LAMBDA=0.0612279

    + NFS=1E+12 NEFF=1.001 NSS=1E+11 TPG=-1.0 RSH=120.6

    + CGDO=4.3E-10 CGSO=4.3E-10 CJ=0.0005 MJ=0.5052

    + CJSW=1.349E-10 MJSW=0.2417 PB=0.64

     

    .ENDS INVERTER

     

    .SUBCKT NAND NDNIN1 NDNIN2 NDNOUT NDNPS NDNGND

    MN1 NDNOUT NDNIN1 NDNPS  NDNPS  PMOS W=15u L=3u

    MN2 NDNOUT NDNIN2 NDNPS  NDNPS  PMOS W=15u L=3u

    MN3 NDNOUT NDNIN2 10     NDNGND NMOS W= 6u L=3u

    MN4 10     NDNIN1 NDNGND NDNGND NMOS W= 6u L=3u

     

    * SPICE LEVEL 2 Model for 1.2 mu Process

     

    .MODEL NMOS NMOS LEVEL=2 LD=0.15U TOX=2.0E-7

    + NSUB=5.36726E+15 VTO=0.743469 KP=8.00059E-05 GAMMA=0.543

    + PHI=0.6 U0=655.881 UEXP=0.157282 UCRIT=31443.8

    + DELTA=2.39824 VMAX=55260.9 XJ=0.25U LAMBDA=0.0367072

    + NFS=1E+12 NEFF=1.001 NSS=1E+11 TPG=1.0 RSH=70.00

    + CGDO=4.3E-10 CGSO=4.3E-10 CJ=0.0003 MJ=0.6585

    + CJSW=8.0E-10 MJSW=0.2402 PB=0.58

     

    .MODEL PMOS PMOS LEVEL=2 LD=0.15U TOX=2.0E-7

    + NSUB=4.3318E+15 VTO=-0.738861 KP=2.70E-05 GAMMA=0.58

    + PHI=0.6 U0=261.977 UEXP=0.323932 UCRIT=65719.8

    + DELTA=1.79192 VMAX=25694 XJ=0.25U LAMBDA=0.0612279

    + NFS=1E+12 NEFF=1.001 NSS=1E+11 TPG=-1.0 RSH=120.6

    + CGDO=4.3E-10 CGSO=4.3E-10 CJ=0.0005 MJ=0.5052

    + CJSW=1.349E-10 MJSW=0.2417 PB=0.64

     

    .ENDS NAND

     

    .SUBCKT JKFF FFJ FFK FFEN FFQ FFQb FFPS FFGND

    * Qb = Qbar

    XJK1 FFJ  FFEN    3  FFPS FFGND NAND

    XJK2 FFK  FFEN    4  FFPS FFGND NAND

    XJK3   3  FFQb  FFQ  FFPS FFGND NAND

    XJK4   4  FFQ   FFQb FFPS FFGND NAND

     

    .ENDS JKFF

     

    .SUBCKT DFF FFD FFWR FFQ FFQb FFPS FFGND

    * D flipflop with data lock on falling clock edge

    XD1 FFD   FFDb   FFPS  FFGND INVERTER

    XD2 FFWR  FFWRb  FFPS  FFGND INVERTER

    XD3 FFD   FFDb   FFWR   11   12 FFPS FFGND JKFF

    XD4  11     12   FFWRb FFQ FFQb FFPS FFGND JKFF

     

    .ENDS DFF

    .ENDS AD8253

     

     

    • Post Points: 5
  • Mon, Aug 5 2013 6:18 AM

    • alokt
    • Top 25 Contributor
    • Joined on Thu, Aug 21 2008
    • Noida, Uttar Pradesh
    • Posts 241
    • Points 3,470
    Re: Name on .ENDS does not match .SUBCKT Reply

    I am not sure if you need to edit pin numbers or order. I do not see a need for that. In order to simulate this model, I would recommend following steps

    1. Edit AD8253.Cir file to move all .subckt outside the main subcircuit definition. This can be done by moving last " .ENDS AD8253" statement to just before the start of .SUBCKT INVERTER .... line (I have attached modified .lib file below) an dsave this as .LIB file

    2. Open this modified lib file in Model Editor & create Symbol for this .lib (Refer "Importing Spice Models" Appendix C under PSpice User Guide)

    3. Use this symbol (AD8253) in your circuit/schematic and include AD8253.lib in your simulation profile.

    Now simulation should work. Hope this helps.

    Here is the modified lib (After doing modification mentioned in Step #1 above)

    * AD8253 SPICE Macromodel          Rev. D 5/2011
    *     JCH / ADI
    * Temperature variations for the AD8253 are NOT included
    * in this model.
    *
    * Voltage Noise parameters for this model will closely model
    * typical AD8253 characteristics.  Current Noise parameters
    * will be slightly higher than typical AD8253 characteristics
    * due to modeling limitations. 
    * Noise is not modeled in Multisim.
    *                     non-inverting input
    *                     |   inverting input
    *                     |   |   A0 (digital gain control)
    *                     |   |   |  A1 (digital gain control)
    *                     |   |   |  |  Digital Write
    *                     |   |   |  |  |   positive supply
    *                     |   |   |  |  |   |  negative supply
    *                     |   |   |  |  |   |  |  output
    *                     |   |   |  |  |   |  |  |   reference
    *                     |   |   |  |  |   |  |  |   |   digital ground
    *                     |   |   |  |  |   |  |  |   |   |
    .SUBCKT AD8253       IN+ IN- A0 A1 WR* 99 50 OUT REF DGND
    .MODEL QPI PNP(VAF=100)
    .MODEL DOUT D(IS=5E-12)
    .MODEL DX D(IS=1E-16)
    .MODEL DNOI1 D(AF=1.5, KF=2E-10)
    .MODEL SWIA VSWITCH(VON=1.5,VOFF=1.2,ROFF=1E8)
    .MODEL SWBP VSWITCH(VON=3,VOFF=2.7)
    *
    * Resistor fb network, output amp
    *
    R3     104 202 10k
    R4     103 201 10k
    R5     201 OUT 10k
    R6     202 REF 10k
    *
    * DIGITAL CONTROL FOR GAIN SETTING
    * Settings are as given in AD8253 ds,
    * Table 5
    * A1 = A0 = 0,    G = 1
    * A1 = 0, A0 = 1, G = 10
    * A1 = 1, A0 = 0, G = 100
    * A1 = 1, A0 = 1, G = 1000
    *
    * DIGITAL CONTROLS ARE ASSUMED TO BE +5V
    * AND 0V. BEHAVIOR WITH OTHER DIGITAL INPUT
    * VOLTAGES IS NOT CHARACTERIZED.
    *
    * Digital power supply
    *
    VDD D99 0 5V
    *
    * Falling clock edge data latches with
    * switches. If WR* is higher than -1.5V,
    * switches pass latched data through, which
    * is latched on falling clock edge.
    *
    XA0 A0  WR*    A0LAT    A0bLAT D99 DGND DFF
    XA1 A1  WR*    A1LAT    A1bLAT D99 DGND DFF
    Vcntlin 0      cntlV    3V
    SLAT0   A0LAT  A0int    WR* cntlV SWIA
    SLAT1   A0bLAT A0barint WR* cntlV SWIA
    SLAT2   A1LAT  A1int    WR* cntlV SWIA
    SLAT3   A1bLAT A1barint WR* cntlV SWIA
    *
    * Switches for bypassing flipflops
    * If WR* is less than -3V, flipflops are
    * bypassed and A0 and A1 are passed
    * directly through.
    *
    SBP0   A0    A0int    0   WR* SWBP
    SBP1   A0bar A0barint 0   WR* SWBP
    XA0bar A0    A0bar    D99 DGND INVERTER
    SBP2   A1    A1int    0   WR* SWBP
    SBP3   A1bar A1barint 0   WR* SWBP
    XA1bar A1    A1bar    D99 DGND INVERTER
    *
    * GAIN CONTROL
    *
    * G = 1
    *
    SGC1  Rg- 105  A0barint 0 SWIA
    SGC2  105 103  A1barint 0 SWIA
    SGC3  106 Rg+  A0barint 0 SWIA
    SGC4  104 106  A1barint 0 SWIA
    *
    * G = 10
    *
    Rfb10a  103 107  6.75k
    Rfb10b  107 108  1.50k
    Rfb10c  108 104  6.75k
    SGC5    Rg- 109  A0int    0 SWIA
    SGC6    109 107  A1barint 0 SWIA
    SGC7    110 Rg+  A0int    0 SWIA
    SGC8    108 110  A1barint 0 SWIA
    *
    * G = 100
    *
    Rfb1e2a 103 111  19.8k
    Rfb1e2b 111 112  400
    Rfb1e2c 112 104  19.8k
    SGC9    Rg- 113  A0barint 0 SWIA
    SGC10   113 111  A1int    0 SWIA
    SGC11   114 Rg+  A0barint 0 SWIA
    SGC12   112 114  A1int    0 SWIA
    *
    * G = 1000
    *
    Rfb1e3a 103 115  49.95k
    Rfb1e3b 115 116  100
    Rfb1e3c 116 104  49.95k
    SGC13   Rg- 117  A0int 0 SWIA
    SGC14   117 115  A1int 0 SWIA
    SGC15   118 Rg+  A0int 0 SWIA
    SGC16   116 118  A1int 0 SWIA
    *
    * INTERNAL VOLTAGE REFERENCE
    *
    RREF1 99 90  500k
    RREF2 90 50  500k
    CREF1 90  0  5uF
    EREF1 98  0  90 0 1
    *
    * CURRENT CONSUMPTION CORRECTION
    *
    ICORR+ 99  0 1.6m
    ICORR-  0 50 1.5m
    *
    * INPUT STAGE COMPARE AMPLIFIER #1
    *
    Q1A        A4   A3  A01  QPI
    Q2A        A6   A9  A2   QPI
    RE1A       A01  A8  415
    RE2A       A2   A8  415
    RC1A       A5   A4  5k
    RC2A       A5   A6  5k
    VADJA      50   A5  1.5V
    IBIASA     99   A8  1m
    * Bias current compensation
    VBIASMONA A10   A3   0V
    FBIASCMPA   0   IN- VBIASMONA 0.9988
    * noise, -PS, offset V introduction
    ENOISA     IN-  A11  A53 98 1
    VOSA       A11  A10  158uV
    EPSRA-     Rg-  A7   98 A62 1
    VPSRA-     A7   A9  140.8uV
    D1A        IN-  99   DX
    D2A        50   IN-   DX
    *
    * VOLTAGE NOISE STAGE COMP AMP #1
    *
    DN1A    A51 A52 DNOI1
    VN1A    A51  98 0.615
    VMEASA  A52  98 0
    RNOI1A  A52  98 3e-4
    *
    F1A     A53 98 VMEASA 1
    RNOI2A  A53 98 1
    *
    * -PS PERTURBATION STAGE COMP AMP #1
    *
    EPSA1   A61  98 50 0 1
    RPSA1   A61 A62 100K
    RPSA2   A62  98 0.15
    CPSA1   A61 A62 450p
    *
    * GAIN STAGE WITH DOMINANT POLE = 0.8Hz COMP AMP #1
    *
    GP2A   A21  98 A6 A4 1
    RP2A   A21  98 1E7
    CP2A   A21  98 2e-8
    *
    * VOLTAGE LIMITING CIRCUITRY COMP AMP #1
    *
    VLIM1A    99 A23 1.5
    DOUT1A   A21 A23 DOUT
    VLIM2A   A24  50 1.75
    DOUT2A   A24 A21 DOUT
    *
    * SUPPLY CURRENT ADJUSTMENT COMP AMP #1
    *
    FADJ1A  0 99 VLIM1A 1
    FADJ2A 50  0 VLIM2A 1
    *
    * INTERMEDIATE GAIN STAGE COMP AMP #1
    *
    GP3A   A22  98 A21 98 1E-3
    RP3A   A22  98 1k
    *
    * CURRENT LIMITING COMP AMP #1
    *
    DILIM1A A22 A25 DOUT
    VILIM1A A31 A25 0.415
    DILIM2A A26 A22 DOUT
    VILIM2A A26 A31 0.415
    *
    * OUTPUT STAGE COMP AMP #1
    * Node 103 = CA #1 output node
    *
    VMO1A     99 A40   0
    VMO2A    A42  50   0
    VMO3A    A31 103   0
    ROUT1A   A40 A31  10
    ROUT2A   A42 A31  10
    GOUT1A   A31 A40  99 A22 0.1
    GOUT2A   A42 A31 A22  50 0.1
    *
    * INPUT STAGE COMPARE AMPLIFIER #2
    *
    Q1B     B4  B3  B1   QPI
    Q2B     B6  Rg+ B2   QPI
    RE1B    B1  B8  415
    RE2B    B2  B8  415
    RC1B    B5  B4  5k
    RC2B    B5  B6  5k
    VADJB   50  B5  1.5V
    IBIASB  99  B8  1m
    * Bias current compensation
    VBIASMONB B10 B3 0V
    FBIASCMPB 0 IN+ VBIASMONB 0.9988
    * CM, +PS, noise introduction
    ECMB3  IN+  B7   B62 98 1
    ENOISB  B7  B9   B53 98 1
    EPSRB+  B9  B10  B64 98 1
    D1B     IN+ 99  DX
    D2B     50  IN+  DX
    *
    * VOLTAGE NOISE STAGE COMP AMP #2
    *
    DN1B    B51 B52 DNOI1
    VN1B    B51 98  0.615
    VMEASB  B52 98  0
    RNOI1B  B52 98  3e-4
    *
    F1B     B53 98 VMEASB 1
    RNOI2B  B53 98 1
    *
    * CM VOLTAGE STAGE COMP AMP #2
    * zero at 31kHz
    *
    ECMB1   B60  98 IN+ 98 1
    ECMB2   B61 B60 IN- 98 1
    RCMB1   B61 B62 100K
    CCMB1   B61 B62 50p
    RCMB2   B62  98 0.19
    *
    * +PS PERTURBATION STAGE COMP AMP #2
    *
    EPSB1   B63  98 99 0 1
    RPSB1   B63 B64 100K
    RPSB2   B64  98 0.1
    CPSB1   B63 B64 100p
    *
    * GAIN STAGE WITH DOMINANT POLE COMP AMP #2
    *
    GP2B   B21  98 B6 B4 1
    RP2B   B21  98 1E7
    CP2B   B21  98 2e-8
    *
    * VOLTAGE LIMITING CIRCUITRY COMP AMP #2
    *
    VLIM1B    99 B23 1.5
    DOUT1B   B21 B23 DOUT
    VLIM2B   B24  50 1.75
    DOUT2B   B24 B21 DOUT
    *
    * SUPPLY CURRENT ADJUSTMENT COMP AMP #2
    *
    FADJ1B  0 99 VLIM1B 1
    FADJ2B 50  0 VLIM2B 1
    *
    * INTERMEDIATE GAIN STAGE COMP AMP #2
    *
    GP3B   B22  98 B21 98 1E-3
    RP3B   B22  98 1k
    *
    * CURRENT LIMITING COMP AMP #2
    *
    DILIM1B B22 B25 DOUT
    VILIM1B B31 B25 0.415
    DILIM2B B26 B22 DOUT
    VILIM2B B26 B31 0.415
    *
    * OUTPUT STAGE COMP AMP #2
    * Node 104 = CA #2 output node
    *
    VMO1B     99 B40   0
    VMO2B    B42  50   0
    VMO3B    B31 104   0
    ROUT1B   B40 B31  10
    ROUT2B   B42 B31  10
    GOUT1B   B31 B40  99 B22 0.1
    GOUT2B   B42 B31 B22  50 0.1
    *
    * INPUT STAGE OUTPUT AMPLIFIER
    *
    Q1C    C4   C3   C1  QPI
    Q2C    C6  C11   C2  QPI
    RE1C   C1   C8  175
    RE2C   C2   C8  175
    RC1C   50   C4  5.75k
    RC2C   50   C6  5.75k
    CC1C   C4   C6  0.7p
    *
    * Introduces second pole
    * P2 = 1/(2*PI*2Rc*Cc1)
    *
    * Offset V, CM, PS, voltage noise introduction
    *
    EPSRC+ 202   C9  C64 98 1
    ECMC3   C9   C7  C62 98 1
    ENOISC  C7   C5  C53 98 1
    VOSC    C5   C3  642.5uV
    EPSRC- 201  C12  C66 98 1
    VPSRC- C12  C11  58.5uV
    D1C     C3   99  DX
    D2C     50   C3  DX
    IBIASC  99   C8  1m
    *
    * VOLTAGE NOISE STAGE OUTPUT AMP
    *
    DN1C   C51 C52 DNOI1
    VN1C   C51  98 0.648
    VMEASC C52  98 0
    RNOI1C C52  98 1.1e-4

    F1C    C53  98 VMEASC 1
    RNOI2C C53  98 1
    *
    * CM VOLTAGE STAGE OUTPUT AMP
    * zero at 3kHz
    *
    ECMC1   C60  98 IN+ 98 1
    ECMC2   C61 C60 IN- 98 1
    RCMC1   C61 C62 100K
    CCMC1   C61 C62 520p
    RCMC2   C62  98 0.29
    *
    * +PS PERTURBATION STAGE OUTPUT AMP
    *
    EPSC1   C63  98 99 0 1
    RPSC1   C63 C64 100K
    RPSC2   C64  98 0.39
    CPSC1   C63 C64 380p
    *
    * -PS PERTURBATION STAGE OUTPUT AMP
    *
    EPSC2   C65  98 50 0 1
    RPSC3   C65 C66 100K
    RPSC4   C66  98 0.39
    CPSC2   C65 C66 20n
    *
    * GAIN STAGE WITH DOMINANT POLE = 65mHz OUTPUT AMP
    *
    GP2C   C21 98 C6 C4 1
    RP2C   C21 98 1E7
    CP2C   C21 98 2.8E-7
    *
    * VOLTAGE LIMITING CIRCUITRY OUTPUT AMP
    *
    VLIM1C    99 C23 1.96
    DOUT1C   C21 C23 DOUT
    VLIM2C   C24  50 2.1
    DOUT2C   C24 C21 DOUT
    *
    * SUPPLY CURRENT ADJUSTMENT OUTPUT AMP
    *
    FADJ1C  0 99 VLIM1C 1
    FADJ2C 50  0 VLIM2C 1
    *
    * INTERMEDIATE GAIN STAGE OUTPUT AMP
    *
    GP3C   C22  98 C21 98 1E-3
    RP3C   C22  98 1k
    CP3C   C22  98 4pF
    *
    * CURRENT LIMITING OUTPUT AMP
    *
    DILIM1C C22 C25 DOUT
    VILIM1C C31 C25 0.415
    DILIM2C C26 C22 DOUT
    VILIM2C C26 C31 0.415
    *
    * OUTPUT STAGE OUTPUT AMP
    *
    VMO1C     99 C40   0
    VMO2C    C42  50   0
    VMO3C    C31 OUT   0
    ROUT1C   C40 C31  10
    ROUT2C   C42 C31  10
    GOUT1C   C31 C40  99 C22 0.1
    GOUT2C   C42 C31 C22  50 0.1
    .ENDS AD8253
    *
    * DIGITAL CONTROLS
    *
    .SUBCKT INVERTER IIN IOUT IPS IGND
    MI1 IOUT IIN IPS  IPS   PMOS W=15u L=3u
    MI2 IOUT IIN IGND IGND  NMOS W= 6u L=3u

    .MODEL NMOS NMOS LEVEL=2 LD=0.15U TOX=2.0E-7
    + NSUB=5.36726E+15 VTO=0.743469 KP=8.00059E-05 GAMMA=0.543
    + PHI=0.6 U0=655.881 UEXP=0.157282 UCRIT=31443.8
    + DELTA=2.39824 VMAX=55260.9 XJ=0.25U LAMBDA=0.0367072
    + NFS=1E+12 NEFF=1.001 NSS=1E+11 TPG=1.0 RSH=70.00
    + CGDO=4.3E-10 CGSO=4.3E-10 CJ=0.0003 MJ=0.6585
    + CJSW=8.0E-10 MJSW=0.2402 PB=0.58

    .MODEL PMOS PMOS LEVEL=2 LD=0.15U TOX=2.0E-7
    + NSUB=4.3318E+15 VTO=-0.738861 KP=2.70E-05 GAMMA=0.58
    + PHI=0.6 U0=261.977 UEXP=0.323932 UCRIT=65719.8
    + DELTA=1.79192 VMAX=25694 XJ=0.25U LAMBDA=0.0612279
    + NFS=1E+12 NEFF=1.001 NSS=1E+11 TPG=-1.0 RSH=120.6
    + CGDO=4.3E-10 CGSO=4.3E-10 CJ=0.0005 MJ=0.5052
    + CJSW=1.349E-10 MJSW=0.2417 PB=0.64

    .ENDS INVERTER

    .SUBCKT NAND NDNIN1 NDNIN2 NDNOUT NDNPS NDNGND
    MN1 NDNOUT NDNIN1 NDNPS  NDNPS  PMOS W=15u L=3u
    MN2 NDNOUT NDNIN2 NDNPS  NDNPS  PMOS W=15u L=3u
    MN3 NDNOUT NDNIN2 10     NDNGND NMOS W= 6u L=3u
    MN4 10     NDNIN1 NDNGND NDNGND NMOS W= 6u L=3u

    * SPICE LEVEL 2 Model for 1.2 mu Process

    .MODEL NMOS NMOS LEVEL=2 LD=0.15U TOX=2.0E-7
    + NSUB=5.36726E+15 VTO=0.743469 KP=8.00059E-05 GAMMA=0.543
    + PHI=0.6 U0=655.881 UEXP=0.157282 UCRIT=31443.8
    + DELTA=2.39824 VMAX=55260.9 XJ=0.25U LAMBDA=0.0367072
    + NFS=1E+12 NEFF=1.001 NSS=1E+11 TPG=1.0 RSH=70.00
    + CGDO=4.3E-10 CGSO=4.3E-10 CJ=0.0003 MJ=0.6585
    + CJSW=8.0E-10 MJSW=0.2402 PB=0.58

    .MODEL PMOS PMOS LEVEL=2 LD=0.15U TOX=2.0E-7
    + NSUB=4.3318E+15 VTO=-0.738861 KP=2.70E-05 GAMMA=0.58
    + PHI=0.6 U0=261.977 UEXP=0.323932 UCRIT=65719.8
    + DELTA=1.79192 VMAX=25694 XJ=0.25U LAMBDA=0.0612279
    + NFS=1E+12 NEFF=1.001 NSS=1E+11 TPG=-1.0 RSH=120.6
    + CGDO=4.3E-10 CGSO=4.3E-10 CJ=0.0005 MJ=0.5052
    + CJSW=1.349E-10 MJSW=0.2417 PB=0.64

    .ENDS NAND

    .SUBCKT JKFF FFJ FFK FFEN FFQ FFQb FFPS FFGND
    * Qb = Qbar
    XJK1 FFJ  FFEN    3  FFPS FFGND NAND
    XJK2 FFK  FFEN    4  FFPS FFGND NAND
    XJK3   3  FFQb  FFQ  FFPS FFGND NAND
    XJK4   4  FFQ   FFQb FFPS FFGND NAND

    .ENDS JKFF

    .SUBCKT DFF FFD FFWR FFQ FFQb FFPS FFGND
    * D flipflop with data lock on falling clock edge
    XD1 FFD   FFDb   FFPS  FFGND INVERTER
    XD2 FFWR  FFWRb  FFPS  FFGND INVERTER
    XD3 FFD   FFDb   FFWR   11   12 FFPS FFGND JKFF
    XD4  11     12   FFWRb FFQ FFQb FFPS FFGND JKFF

    .ENDS DFF

     

     

    • Post Points: 5
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Started by 1PS1 at 23 Jun 2010 10:00 AM. Topic has 7 replies.