Home > Community > Forums > PCB Design > 16.0 Autorouter ignoring constraints

Email

* Required Fields

Recipients email * (separate multiple addresses with commas)

Your name *

Your email *

Message *

Contact Us

* Required Fields
First Name *

Last Name *

Email *

Company / Institution *

Comments: *

 16.0 Autorouter ignoring constraints 

Last post Tue, Jun 29 2010 12:33 PM by sharted. 1 replies.
Started by sharted 22 Jun 2010 10:41 AM. Topic has 1 replies and 956 views
Page 1 of 1 (2 items)
Sort Posts:
  • Tue, Jun 22 2010 10:41 AM

    • sharted
    • Top 500 Contributor
    • Joined on Wed, Jun 16 2010
    • Posts 19
    • Points 320
    16.0 Autorouter ignoring constraints Reply

     

     hello all,

     

    I am fairly new to Allegro (16.0), so bear with me.  I am trying to use the autorouter, and it is killing me.  first, it wont connect VCC and GND nets to my VCC and GND planes, even though the autorouter says it's 100% complete.  second, it is ignoring my constrains when it autoroutes.  it will run traces right over pads, and put vias straight through internal traces.  what gives?  I set my spacing to be at least 10mil (some things are 12+). 

     here is an image of what autorouter does to me: http://img824.imageshack.us/img824/7008/constraintwtf.jpg

     

    also, does anyone know why my silkscreen layer does not always move with my components when I move an entire group?  the silkscreen moves twice as far in a given direction as the rest of the parts, but only when I select multiple parts.

     

    Thanks for any help
    • Post Points: 5
  • Tue, Jun 29 2010 12:33 PM

    • sharted
    • Top 500 Contributor
    • Joined on Wed, Jun 16 2010
    • Posts 19
    • Points 320
    Re: 16.0 Autorouter ignoring constraints Reply

    ok, so the VCC and GND was a problem with the property no_route being set.  I am not sure how it got set, but eliminating that property fixed the problem.

     

    I still have a problem of it ignoring the constrainst.  in every case I can find on my board, the autorouter has room to place vias and traces in the right locations, but it simply chooses to violate the constrains and put them too close.  here is the "Show Element" file for one of the the DRC errors:

     

    LISTING: 1 element(s)

               < DRC ERROR >          

      Class:           DRC ERROR CLASS
      Subclass:        TOP
      Origin xy:       (6830.0 2646.2)
      Constraint:      SMD Pin to Thru Via Spacing
      Constraint Set:  DEFAULT
      Constraint Type: NET SPACING CONSTRAINTS

      Constraint value: 18 MIL
      Actual value:     11 MIL

      - - - - - - - - - - - - - - - - - - - -
      Element type:    SYMBOL PIN
      Class:           PIN

      PIN:          C59.2
      pinuse:       UNSPEC
      location-xy:  (6800.0 2640.0)
      part of net name:  N633505
      - - - - - - - - - - - - - - - - - - - -
      Element type:    VIA
      Class:           VIA CLASS

      origin-xy:    (6842.0 2646.2)

      part of net name:  NTDS2_P0_2
      Connected lines:     2 ( TOP IS6 )

      padstack name:   VIA

      padstack defined from TOP to BOTTOM
      rotation:  0.000  degrees
      via is not mirrored

      - - - - - - - - - - - - - - - - - - - -

    • Post Points: 5
Page 1 of 1 (2 items)
Sort Posts:
Started by sharted at 22 Jun 2010 10:41 AM. Topic has 1 replies.