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 Verilog simulation using verilog XL  

Last post Mon, Apr 22 2013 9:59 AM by tstark. 2 replies.
Started by OLyonnais 09 Jun 2010 06:10 AM. Topic has 2 replies and 2366 views
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  • Wed, Jun 9 2010 6:10 AM

    • OLyonnais
    • Top 500 Contributor
    • Joined on Mon, Mar 22 2010
    • Posts 17
    • Points 295
    Verilog simulation using verilog XL Reply

     Hi,

    i want to simulate a sample MUX21 realised on my schematic. I think, before going on the verilog XL , i need to put a load capacitor (classical cap) at the output to be able to see my output signal Z.

    Then, arrived on the verilog XL interface, when i lauch the simulation, i have this following error:

     

    *************************on the icfb terminal; *****************************************

    \o ---------- Begin Netlist Configuration Info ----------
    \o                 (incremental data only)
    \o
    \o CELL NAME                   VIEW NAME            NOTE            
    \o ---------                   ---------            ----            
    \o
    \o cap                         symbol               *Stopping View* 
    \o nsvtlp                      verilog              *Stopping View* 
    \o psvtlp                      verilog              *Stopping View* 
    \o MUX21                    schematic                            

     

     

    ******************************on the verilog XL terminal *************************************

     Message!  deleted TMS file 'verilog.tms' due to error in                       
              input file                                                           
                                                               [Verilog]

    Error!    Module or primitive (cap) not defined            [Verilog-MOPND]     
              "ihnl/cds0/netlist", 19: cap C0(.MINUS(                              
              cds_globals.gnd_), .PLUS(Z));
    1 error
    End of Tool:    VERILOG-XL    08.20.001-p   Jun  9, 2010  15:03:34

    ****************************************************************

     

    is the problem comes from to the view name of the capacity?  

    thank you 

     

     

    • Post Points: 20
  • Sun, Apr 21 2013 1:27 AM

    • PranR
    • Not Ranked
    • Joined on Sun, Apr 21 2013
    • Posts 1
    • Points 20
    Re: Verilog simulation using verilog XL Reply

    Hi ,

              I am getting the error while simulating the Verilog  in cadence which is integrated with an inverter block made from nmos_hvt and pmos_hvt of PDK library. verilog is a symbol generated in cadence from the verilog file.

     

    Error!    Module or primitive (verilog) not defined            [Verilog-MOPND]     
              "ihnl/cds0/netlist", 35:verilog  I12(net17,                             
             net15 , net21 , net19, net012, O1, O2, O3);

    Error!    Module or primitive (inverter) not defined            [Verilog-MOPND]     
              "ihnl/cds0/netlist", 36:inverter  I13(.out(                             
             output_) , .in(net012)) ;

     Help !

    Thanks 

    • Post Points: 20
  • Mon, Apr 22 2013 9:59 AM

    • tstark
    • Top 200 Contributor
    • Joined on Mon, Jul 28 2008
    • San Jose, CA
    • Posts 40
    • Points 455
    Re: Verilog simulation using verilog XL Reply

    Hi, PranR.

    The modules "verilog" and "inverter" are not defined in your run for some reason. You need to read in the definition for the simulator to resolve the modules. It seems like you are using an integrated environment. Unfortunately I can only comment about the Verilog error.

    The code will look like:

    module verilog (in0,in1,out0,out1,clk,rstn);

    If it is not defined then you will get an error.

    Also, please start a new thread for a new topic rather than replying to an old thread.

     

    -ts

    • Post Points: 5
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Started by OLyonnais at 09 Jun 2010 06:10 AM. Topic has 2 replies.