Home > Community > Forums > Functional Verification > Elaborate Verilog and VHDL mixed language design

Email

* Required Fields

Recipients email * (separate multiple addresses with commas)

Your name *

Your email *

Message *

Contact Us

* Required Fields
First Name *

Last Name *

Email *

Company / Institution *

Comments: *

 Elaborate Verilog and VHDL mixed language design 

Last post Mon, May 17 2010 3:36 PM by Ruchir. 0 replies.
Started by Ruchir 17 May 2010 03:36 PM. Topic has 0 replies and 2668 views
Page 1 of 1 (1 items)
Sort Posts:
  • Mon, May 17 2010 3:36 PM

    • Ruchir
    • Not Ranked
    • Joined on Thu, Jan 21 2010
    • Sunnyvale, CA
    • Posts 1
    • Points 5
    Elaborate Verilog and VHDL mixed language design Reply

     I have VHDL design files and my top module is in Verilog.

    i am using this command to compile and elaborate the design

        ncvhdl -work work -messages gate_10.vhd
        ncvhdl -work work -messages dff.vhd  
        ncvlog -work work -messages lfsr_gate_mixed1.v   
        ncvlog -work work -messages lfsr_tb1.v

        ncelab -work work -messages -access +rwc +mixedlang work.lfsr_tb1

    when i try to elaborate the design i get this error 

    ncelab: *E,CUVMUR (./lfsr_gate_mixed1.v,9|6): instance 'lfsr_tb1.L1@lfsr_gate_mixed1<module>.D1' of design unit 'dff1' is unresolved in 'work.lfsr_gate_mixed1:module'.

    ncelab: *W,CUDEFB: default binding occurred for component instance (lfsr_tb1.L1@lfsr_gate_mixed1<module>.G1) with design unit (WORK.GATE_10:GATE10_ARCH).

     what am i doing wrong??

    • Post Points: 5
Page 1 of 1 (1 items)
Sort Posts:
Started by Ruchir at 17 May 2010 03:36 PM. Topic has 0 replies.