I assume that you're talking about Verilog rather than VHDL here!
It sounds like you are looking for the functionality provided by the "libmap" which is Verilog's equivalent to VHDL configurations.
You provide a libmap file to the compiler (ncvlog/ncelab or irun) which tells it which *.v files go into which compiled libraries, and also which instances use which modules/libraries.
I've not used it much myself, but it's well enough documented that you should be able to find your way.
Fire up cdnshelp, and search for \-libmap (note: the back-slash is needed in front of the dash).