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 System Verilog with Spice *F,INTERR - cu_check_port_var_aca 

Last post Wed, Apr 14 2010 5:06 PM by StephenH. 1 replies.
Started by GraemeNunn 12 Apr 2010 04:29 PM. Topic has 1 replies and 1789 views
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  • Mon, Apr 12 2010 4:29 PM

    • GraemeNunn
    • Not Ranked
    • Joined on Mon, Apr 12 2010
    • Posts 1
    • Points 20
    System Verilog with Spice *F,INTERR - cu_check_port_var_aca Reply

    Hi,

    I am trying to use a system verilog testbench to verify a spice block. The aim is to have system verilog stimulus and monitoring using real values.I have example with the stimulus side working but not the monitoring.

    When I run my simple example I receive the following error during elaboration. What am I missing from the configuration to get this working?

     

    (This testcase started off as the spice_in_middle example from the AMSD workshop)

    Thanks

    Graeme Nunn

     ncelab: *F,INTERR: INTERNAL ERROR
    -----------------------------------------------------------------
    The tool has encountered an unexpected condition and must exit.
    Contact Cadence Design Systems customer support about this
    problem and provide enough information to help us reproduce it,
    including the logfile that contains this error message.
      TOOL: ncelab  08.20-s009
      HOSTNAME:
      OPERATING SYSTEM: Linux 2.6.9-89.0.20.ELsmp #1 SMP Mon Jan 18 12:19:33 EST 2010 x86_64
      MESSAGE: cu_check_port_var_aca - not net, class 520, file: top.sv, line:6

     Input Files:

    ------------------------ 
    Run
    ------------------------ 
    #! /bin/csh -f

    irun    *.sv \
            *.vams \
            amscf.scs \
            -timescale 1ns/100ps \
            -mess

    ----------------------
    pot.sp
    ----------------------
    .subckt pot rtop rmid
    r1 rtop rmid 10k
    r2 rmid 0 10k
    .ends

    ----------------------
    top.sv
    ----------------------
    module top ;

      timeunit      1ns ;
      timeprecision 1ns ;

      harness h1 (.resp(out),.sig(sig));
      pot p1 (.rtop(sig),.rmid(out));

    endmodule : top
    ----------------------
    harness.sv
    ----------------------
    module harness (resp,sig);
            output real  sig ;
            input var real resp ;

            var real sig_r;
            assign sig=sig_r;

            initial begin
                    sig_r=0.0;
                    #10 sig_r=1.0;
                    #10 sig_r=2.0;
                    #10 sig_r=3.0;
                    #10 sig_r=2.0;
                    #10 sig_r=1.0;
                    $finish;
            end

            always @(resp) $display("Resp has changed to %0f",resp);

    endmodule

    ----------------------
    amscf.scs
    ----------------------
    include "./pot.sp"

    * AMS Control file
    include "top.scs"
    amsd {
            portmap subckt=pot file="pot.pb"
            config cell=pot use=spice
            ie vsup=1.8
    }

    ----------------------
    top.scs
    ----------------------
    simulator lang=spectre
    rawFmtOpt options rawfmt=sst2fbin   maxwarnstologfile=1000 maxnotestologfile=1000
    saveNodes options save=all
    timeDom tran stop= 30us
    ----------------------
    pot.pb
    ----------------------
     //*** pot.pb ***
    //* Portbind file for:
    //* SPICE subckt pot : HDL module pot
    //* SPICE port  :       HDL port        :       HDL Parameters

    rtop    :       rtop    :       dir=inout
    rmid    :       rmid    :       dir=inout


     

    • Post Points: 20
  • Wed, Apr 14 2010 5:06 PM

    • StephenH
    • Top 25 Contributor
    • Joined on Tue, Sep 2 2008
    • Bristol, Avon
    • Posts 278
    • Points 4,450
    Re: System Verilog with Spice *F,INTERR - cu_check_port_var_aca Reply

    Hi Graeme.

    I tried to reproduce this from the files that you pasted into your post, but either you missed some *.vams files, or the irun command is wrong.

    Since the error message is an internal error (*F,INTERR) in ncelab, it would be helpful if you could open a service request at http://support.cadence.com/ so that the support team can look into this in more detail.

    Cheers.
    Steve

    Steve Hobbs / Applications Engineer / Cadence Functional Verification
    • Post Points: 5
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Started by GraemeNunn at 12 Apr 2010 04:29 PM. Topic has 1 replies.