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 Saving verilog-A variables in UltraSim 

Last post Sat, Feb 20 2010 8:17 AM by Quek. 1 replies.
Started by TonySal 20 Feb 2010 05:46 AM. Topic has 1 replies and 1538 views
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  • Sat, Feb 20 2010 5:46 AM

    • TonySal
    • Not Ranked
    • Joined on Fri, Oct 24 2008
    • Fremont, CA
    • Posts 5
    • Points 85
    Saving verilog-A variables in UltraSim Reply

    I am trying to debug a verilog-A behavioral model, using UltraSim as my simulator.

    How do I tell UltraSim to save the internal variables in my model, so I can view/plot them?

    In Spectre there is an option saveahdlvars=all, but it does not seam to work in UltraSim.

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    • Post Points: 20
  • Sat, Feb 20 2010 8:17 AM

    • Quek
    • Top 10 Contributor
    • Joined on Wed, Oct 14 2009
    • Singapore, 00-SG
    • Posts 1,063
    • Points 16,185
    Re: Saving verilog-A variables in UltraSim Answer Reply
    Hi Tony

    Ultrasim does not have the equivalent of spectre's saveahdlvars. You can use the following instead:

    .probe all(I123)

    where I123 refers to the verilogA instance. The above cmd will save all signals and variables for instance I123. To save a particular variable or signal, you can use:

    .probe my_var_or_sig_name(I123)

    This is also explained in COS solution 11559680. : )

    Best regards
    Quek
    • Post Points: 5
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Started by TonySal at 20 Feb 2010 05:46 AM. Topic has 1 replies.