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 canit able to connect the ports 

Last post Fri, Feb 12 2010 5:55 PM by StephenH. 1 replies.
Started by specmane 12 Feb 2010 04:45 PM. Topic has 1 replies and 1327 views
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  • Fri, Feb 12 2010 4:45 PM

    • specmane
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    • Joined on Wed, Nov 4 2009
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    canit able to connect the ports Reply

    Hi all, I have an OVC OVC_A which has a sigmap signal sig_p : list of bit.

    i need to use this OVC to create other OVC OVC_B which has three diffrent signal consider sig_a ,sig_b ,sig_c.

     In OVC_A the signal is binded as external. so i extended the sigmap and made as empty. and i tried to connect the OVC_A sig_p with OVC_B sig_a ,sig_b and sig_c. and in turn this sig_a ,sig_b and sig_c will be connected to hdl_path() and

     i am getting the error Error: Bound sets cannot have an external inout port with other external ports

    sys.env.OVC_ A.sigmap. sig_p: NULL_SIM inout simple_port of list of bit Also externally connected to agent 'NULL_SIM', using hdl_path() 'signal_a' sys.env.sigmap. sig_a: NULL_SIM inout simple_port of list of bit Also externally connected to agent 'NULL_SIM', using hdl_path() 'signal_a'

     is there any other way to do my intended functionalily i.e signal in the instantiated ovc should be maped to the parent sigmap name?

    Thanks,

    Muthu

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  • Fri, Feb 12 2010 5:55 PM

    • StephenH
    • Top 25 Contributor
    • Joined on Tue, Sep 2 2008
    • Bristol, Avon
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    Re: canit able to connect the ports Reply

    Hi Muthu,

    I'm not sure whether I fully understand your question, so let me re-phrase it and see if I got it right.

    You want to connect the ports of OVC_A to the ports of OVC_B and the ports of OVC_B to the RTL signals?

    If this is your situation, then in fact you can simply constrain the OVC_A hdl_path()s to the RTL signals, and also constrain the hdl_path()s of OVC_B to the same RTL signals. Internally in Specman, the ports are merged if more than one port connects to the same RTL signal.

    Normally you should not need to worry about binding the signal to external, because this is done automatically if you constrain hdl_path() for a port.

    Hope this helps.

    Steve Hobbs / Applications Engineer / Cadence Functional Verification
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Started by specmane at 12 Feb 2010 04:45 PM. Topic has 1 replies.