I have a problem with the LVS.
In my circuit there are some p-MOS with the body (n-well) connected to the source at a potential different from VDD.
1) The LVS gives back some errors on the well. Is it a problem or it can be neglected?
2) There is also another error of the same type related to one of the MOS transistors implemented in such well. It seems that the others are not a problem. How is it possible if they are in the same well??
Thanks a lot,