Home > Community > Forums > Custom IC Design > connections to abstract not verified by Assura LVS - what's wrong?

Email

* Required Fields

Recipients email * (separate multiple addresses with commas)

Your name *

Your email *

Message *

Contact Us

* Required Fields
First Name *

Last Name *

Email *

Company / Institution *

Comments: *

 connections to abstract not verified by Assura LVS - what's wrong? 

Last post Fri, Jan 7 2011 4:23 PM by Quek. 10 replies.
Started by TrevorB 07 Jan 2010 01:53 AM. Topic has 10 replies and 6596 views
Page 1 of 1 (11 items)
Sort Posts:
  • Thu, Jan 7 2010 1:53 AM

    • TrevorB
    • Not Ranked
    • Joined on Mon, Nov 30 2009
    • Huntsville, AL
    • Posts 14
    • Points 250
    connections to abstract not verified by Assura LVS - what's wrong? Reply

    Hi,

    We are using an IP block from our foundry in our chip.  The IP block is located below the top level of the hierarchy.  And, the IP block is presented as an empty layout block, containing only pins and boundary shapes.

    Currently, as we run Assura LVS with the default options, our outside connections to the IP block's pins are not verified. We can swap connections - even leave connections open - but LVS does not complain!  That's no good...

    What do I need to do differently to make Assura LVS verify our connections to the IP block's pins?

    Thanks!

    Trevor

    Filed under: , , ,
    • Post Points: 20
  • Fri, Jan 8 2010 10:15 AM

    • Quek
    • Top 10 Contributor
    • Joined on Wed, Oct 14 2009
    • Singapore, 00-SG
    • Posts 1,019
    • Points 15,485
    Re: connections to abstract not verified by Assura LVS - what's wrong? Reply
    Hi Trevor

    This should not be happening. Assura will verfied connections and pins for blackboxes. If you check design.erc file in the lvs run directory, do you see pins being created for the ip block?

    Would you please provide the following info?
    a. Input layout type: gds2 or df2?
    b. Do pinLayer and pinText cmds exist in extract.rul file?
    c. Output of "assura -W" cmd in a terminal window

    Please see the section "Extracting Cells as Black Box Cells" in the Assura Developer's Guide for more info on blackbox methodology.
    linux>xpdf $ASSURAHOME/doc/assuradev/assuradev.pdf &

    Best regards
    Quek
    • Post Points: 20
  • Sat, Jan 9 2010 12:58 AM

    • TrevorB
    • Not Ranked
    • Joined on Mon, Nov 30 2009
    • Huntsville, AL
    • Posts 14
    • Points 250
    Re: connections to abstract not verified by Assura LVS - what's wrong? Reply

    Hi Quek,

    Thanks for your reply.  To answer your questions:

    1) I cannot find the IP block's cellName even mentioned in the design.erc file.

    2) The layout and schematic are both df2 - no GDS2.

    3) I found the following rules in my extract.rul file:

    ;; 
    ;; >>>>>>>>>>>>>>>>>>>>>>>>>>>>>>
    ;; text layer
    ;;
    POLY1_pintext = textToPin( "PIN" type( "poly1"))
    MET1_pintext = textToPin( "PIN" type( "metal1"))
    MET2_pintext = textToPin( "PIN" type( "metal2"))
    MET3_pintext = textToPin( "PIN" type( "metal3"))
    MET4_pintext = textToPin( "PIN" type( "metal4"))
    PAD_pintext = textToPin( "PIN" type( "pad"))
    ;;
    ;; symbolic pins for macro LVS and RCX
    ;;
    POLY1_sympin = pinLayer( "POLY1" type( "pin"))
    MET1_sympin = pinLayer( "MET1" type( "pin"))
    MET2_sympin = pinLayer( "MET2" type( "pin"))
    MET3_sympin = pinLayer( "MET3" type( "pin"))
    MET4_sympin = pinLayer( "MET4" type( "pin"))

    ;;
    ;; >>>>>>>>>>>>>>>>>>>>>>>>>>>>>>
    ;; pinPurpose layer (only drc)
    ;;
    POLY1_pinPurpose = layer( "POLY1" type( "pin"))
    MET1_pinPurpose = layer( "MET1" type( "pin"))
    MET2_pinPurpose = layer( "MET2" type( "pin"))
    MET3_pinPurpose = layer( "MET3" type( "pin"))
    MET4_pinPurpose = layer( "MET4" type( "pin"))
    PAD_pinPurpose = layer( "PAD" type( "pin"))

    Using this PDK, for general pin designation, we only have to label the drawing shapes using layer, "PIN", purpose, "<metal_layer>", as indicated above.  However, inside the IP block layout, the pin shape also exists as a df2 "terminal".  So, it should be covered both ways.

    4) The Assura version is:

    $ assura -W
    sub-version 3.2_USR2_HF11

    $ assura -V
    @(#)$CDS: assura version av3.2:Production:dfII5.1.41:5.10.41.500.6.130 06/29/2009 04:29 (logavt05) $

    5) I have read the section you described, plus the related one in the user's guide, and I have tried the following statements in my runs:

    Attempt #1: 

    blackBox("MY_IP_BLOCK_CELL_NAME")

    Attempt #2:

    blackBox("MY_IP_BLOCK_CELL_NAME" sch)
    blackBox("MY_IP_BLOCK_CELL_NAME" lay)

    Strangely, both runs complain about not being able to find the cell in the design hierarchy, although I clearly see the cellName being used in both designs. ... Incidentally, for testing purposes, I am running LVS at a lower level of the chip, in which the IP block exists as a top level cell.  I don't know if that makes a difference...

    Maybe the extract rules need some help, since neither I nor Assura can find the cell in Assura's schematic or layout netlist?

    Thanks!

    Trevor

    Filed under: , , , ,
    • Post Points: 20
  • Sat, Jan 9 2010 6:25 AM

    • Quek
    • Top 10 Contributor
    • Joined on Wed, Oct 14 2009
    • Singapore, 00-SG
    • Posts 1,019
    • Points 15,485
    Re: connections to abstract not verified by Assura LVS - what's wrong? Reply
    Hi Trevor

    Thank you for the detail info. Here is what I think:

    a. Blackbox cell cannot be found by Assura
    - Try using blackbox("cellName viewName libName")

    b. erc file does not contain ip cell name
    - This definitely means that the blackbox pins have not been extracted correctly
    - Check if you have enabled cmds such as ?textPriOnly=t or ?textLevel=0:0
    - Pin must be extracted for the blackbox in order for it to be properly compared
    - Since your extract rule file only contains pinLayer and textToPin cmds, you should ensure that the text origin overlaps the dfII pin shapes. Otherwise the shapes will be extracted without pin names. This is usually not necessary if pinText cmds are present. pinText reads the names of the dfII pins
    - If your current ip block only contains dfII pins and not text, please place the appropriate text over the pins using the pin layer and its corresponding metal purpose

    >>>running LVS at a lower level of the chip, in which the IP block exists as a top level cell.
    I think perhaps what you meant is "running LVS at a lower level of the chip in which the IP block exists as a cell in the top level". This is ok. Blackboxes will work as long as they exist as cells and not as the top level cell being compared.

    The blackbox cell should appear in both schematic and layout netlists. For your case, it should be similar to the following in the layout vnl netlist:

    c "myIPblock layout myLib" BlackBox  VDD P      GND G      IN NONE    avC4 N(f)
     ;;
    * 4 pins
    * 4 nets
    * 0 instances

    In case you are checking the schematic and layout netlists using vldbToCdl cmd in a terminal window, please note that this cmd does not dump out the blackbox cells. Please use vldbToVnl instead:
    unix>vldbToVnl design.ldb > design.ldb.ascii
    unix>vldbToVnl design.sdb > design.sdb.ascii

    For your information, if the contents of the ip block is not important and need not be extracted by lvs, you can also use ?blackBoxCell cmd in avParameters. The difference is that blackBox cmd allows shapes to be extracted normally during lvs and hence even though the ip cell will not be compared, parasitics can subsequently still be extracted from it. ?blackBoxCell only allows pins and some blackbox shapes to be extracted and so the final result is a true blackbox, not only for lvs comparison but also for parasitic extraction.


    Best regards
    Quek
    • Post Points: 20
  • Mon, Jan 11 2010 8:52 PM

    • TrevorB
    • Not Ranked
    • Joined on Mon, Nov 30 2009
    • Huntsville, AL
    • Posts 14
    • Points 250
    Re: connections to abstract not verified by Assura LVS - what's wrong? Reply

    Hi Quek,

    a. I tried using the syntax you suggested for ?blackBox ("cellName viewName libName"), but that did not help.  LVS still passes, even though I switched two connections, deliberately testing for a fail.

    BTW, my IP block does not have a schematic.  We created an empty one to make LVS run to completion.  Was this incorrect?

    b. We do not have ?textPriOnly=t set or ?textLeve=0.0.  Should we?  I verified that the pins are correct in the layout.  (They have drawing, pin shapes, and pin text with pin-text origin over the drawing and pin shapes.)

    Should I check anything else?  I am really stumped.

    BTW, I could not find the blackBox syntax you mentioned in the docs.  Is it documented elsewhere?

    Thanks!

    Trevor

    • Post Points: 20
  • Tue, Jan 12 2010 9:04 AM

    • Quek
    • Top 10 Contributor
    • Joined on Wed, Oct 14 2009
    • Singapore, 00-SG
    • Posts 1,019
    • Points 15,485
    Re: connections to abstract not verified by Assura LVS - what's wrong? Reply

    Hi Trevor

    A cellname can be short (simply the cellname) or long (with view and lib info). Please see the section on "Representing Cell and Device Names" in the Assura Developer's Guide. Actually the correct cmd is :

    blackBox("cellName viewName libName")

    and not:

    ?blackBox ("cellName viewName libName")

    textPriOnly and textLevel need not be used if they are not necessary. I will think more about your question and update you again. Would you please uploaded your log, cls, csm and erc files? Total of 4 files.

    Thanks
    Quek

    • Post Points: 5
  • Wed, Jan 13 2010 1:12 AM

    • TrevorB
    • Not Ranked
    • Joined on Mon, Nov 30 2009
    • Huntsville, AL
    • Posts 14
    • Points 250
    Re: connections to abstract not verified by Assura LVS - what's wrong? Answer Reply

    I spoke with our foundry's support team, and I experimented some more.  I finally got it working.  Here's what I learned:

    1. The black box's schematic cannot be empty.  It must contain at least one device (cds_thru, presistor, some transistor, etc.).  If it does not, Assura LVS will prune it from the netlist, despite the blackBoxCell statement.  We also included the pins.
    2. Any global signals that are pinned out on the layout must also be pinned out on the black box's symbol.  If they are not, then them must be tied to some non-trivial device (cds_thru, presistor, some transistor, etc.) inside the black box's schematic; otherwise, they will not appear on the definition of the black box's pin boundary.
    3. The dummy devices used inside the black box's schematic are of no consequence, since they will be discared as the ignored guts of a "black box".
    4. I ultimately used "blackBoxCell" instead of "blackBox", although I imagine "blackBox" could be used somehow too...

    As an example, here are the guts of our dummy schematic for the black box:

    Dummy Schematic for Black Box block

    Thanks again for the help, Quek!

    HTH,

    Trevor

    Filed under: , , , ,
    • Post Points: 20
  • Wed, Jan 13 2010 9:15 AM

    • Quek
    • Top 10 Contributor
    • Joined on Wed, Oct 14 2009
    • Singapore, 00-SG
    • Posts 1,019
    • Points 15,485
    Re: connections to abstract not verified by Assura LVS - what's wrong? Reply

    Hi Trevor

    It is good to know that the problem has been resolved. Actually your problem no longer exists from Assura41 onwards. Prior to Assura41, it is not possible for Assura to netlist an empty schematic that has only pins. The workaround is to copy the symbol view as "auLvs" view and then change the cdf componentName (Go to cdf form, press "simInfo" button and select auLvs simulator) to the cell name. This will also work, no components are needed inside the empty schematic. Only pins are necessary. I have confirmed what you are observing using Assura32USR2.

    If the latest Assura41USR1_HF3 is used, it is not necessary to create the auLvs view. The empty pins-only schematic will be netlisted correctly. If you have time, maybe you can switch to Assura41USR1_HF3 and give it a try.

    Thank you very much for the detail explanation. I think you have contributed a valuable post to the forum which will be helpful to other users. : )

    Best regards
    Quek

    • Post Points: 35
  • Fri, Jan 7 2011 9:51 AM

    • shumble1
    • Not Ranked
    • Joined on Tue, Mar 3 2009
    • Posts 2
    • Points 25
    Re: connections to abstract not verified by Assura LVS - what's wrong? Reply

    This post was really valuable.  We have been running into the same problem with an empty schematic, but had not yet determined the best method for fixing this problem. 

     

    We are on Assura41USR1_HF14, and the empty pins-only schematic was still not netlisted correctly.  Maybe it was there on HF3, but by the time it got to HF14, it has disappeared again. 

     

    I'm going to try the workaround for copying the symbol to the auLVS view.  This will probably be the best solution for us at this time.

     

    • Post Points: 5
  • Fri, Jan 7 2011 10:01 AM

    • shumble1
    • Not Ranked
    • Joined on Tue, Mar 3 2009
    • Posts 2
    • Points 25
    Re: connections to abstract not verified by Assura LVS - what's wrong? Reply

    Hi Quek,

     

    I tried both HF14 and creating an "auLvs" view and neither of them worked with our cell.

     

    The symbol we use has pins that are busses for example PA<8:0>.  It seems that when Assura runs, it does not recognize any pins that are labeled as busses.  Is there a workaround for this?

    • Post Points: 20
  • Fri, Jan 7 2011 4:23 PM

    • Quek
    • Top 10 Contributor
    • Joined on Wed, Oct 14 2009
    • Singapore, 00-SG
    • Posts 1,019
    • Points 15,485
    Re: connections to abstract not verified by Assura LVS - what's wrong? Reply

    Hi shumble1

    If you are seeing netlisting error due to bus notations for the pins, this issue has already been resolved and the fix is in Assura41USR2. USR2 is the immediate version after Assura41USR1_HF14. You can of course also use the latest version Assura41USR2_HF1. The fix is in it too. Previously Assura is unable to correctly expand a bus notation in cdf "termOrder" property and a workaround was to manually expand it in the cdf form. Eg.

    Original pin name in "termOrder" property in cdf form:
    abc<0:3>

    Workaround:
    abc<0> abc<1> abc<2> abc<3>

    Would you please try Assura41USR2_HF1 to see if it resolves your problem? If it does not, kindly post the Assura log file that contains the error message.

    Thanks
    Quek

    • Post Points: 5
Page 1 of 1 (11 items)
Sort Posts:
Started by TrevorB at 07 Jan 2010 01:53 AM. Topic has 10 replies.