Previously, our layout designers were accustomed to doing a "fit zoom" and viewing the entire chip. At this perspective, with all layout layers set to no-view, they could see all the Assura DRC error markers. (It's an informal tape-out, sign-off test.)
However, for some reason, they can no longer see all the errors. They can only see large clumps of errors, but they have to zoom in to see smaller isolated errors.
I also was accustomed to the principle that any "highlight" was viewable no matter how far the viewer is zoomed out. But, this does not seem to hold true for the highlight markers in Assura 3.2 and IC 220.127.116.110.6.137.
Do you have any suggestions on how to increase the visibility of Assura DRC error markers (highlight shapes)?
BTW, I have experimented with increasing the stipple density and outline width of the highlight-drawingX layers, but that seemed to make matters worse - not better - for the full chip view.