this post isin reference to http://www.cadence.com/community/forums/T/14022.aspx , where i described problems concerning an inductor that had been automatically generated by VPCD tool. Defining the layout of the inductor as a blackBox does not solve the problem, for assura does not recognize pins of the device correctly.
AMS HitKit provides a library SPIRALS containing several inductors. I have analysed one of the layouts, and noticed that the whole spral is placed on a INDDEF and CELBOX layer. The name of the inductor model is on INDDEF layer. The HitKit spirals pass Assura LVS without any errors, so I decided to modify my Inductor Layout in the very same way. Unfortunately even by a very simple layout (actually for test purposes I run LVS for a single inductor connected to ports) LVS fails (reports errors - pins). I get the following errors:
1) Device 'Ind1(IND)' on Schematic is unbound to any Layout device
2) There is an extract problem of a short (pins pp1 and pp2)
3) a compare error - unmatched pins pp1 and pp2 (not present on the layout) - it is funny that B terminal of the inductor is not being reported as unmatched.
4) ERC Warning - INDDEF does not define a correct spiral
5) ERC Warning - illegal layer under spiral (it refers to polisilicon layer building a PSD under the spiral)
I have also looked through the extract.rul file which contains some extractDevice command concerning the HitKit spirals, what suggests describing my spiral in the file.
Any help or suggestions very appreciated.
P.S. I attach zip file containing image of the schematic, and reports of the LVS run (.erc and .cls files)